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HTG13J0 Scheda tecnica(PDF) 13 Page - Holtek Semiconductor Inc |
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HTG13J0 Scheda tecnica(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 30 page ![]() HT13J0 13 May19,1999 An example of an LCD driving waveform (1/8 dutyand1/5bias)isshownbelow. Oscillatorcircuit Only one external resistor is needed for HTG13J0 oscillator circuit. The system clock is also used as the reference sig- nal of LCD driving clock, sound effect clock, and internal TIMER frequency source. One HTG13J0 machine cycle consists of a se- quence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4 ms, if the system frequency is up to 1.0MHz. Inputports PS,PP All ports can have internal pull high resistors determined by mask option. Every bit of the in- put ports PP and PS can be specified to be a trigger source to wake up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALTstatus. Outputport PA0~PA2 A mask option is available to select whether the output is a CMOS or open drain NMOS type. After an initial clear, the output port PA de- faultshighforCMOSorfloatingforNMOS. Note: PA3 controls bit 13 of the program memory. Be careful about PA3. When instruction "OUT PA,A" isoperated,portA ischangedaswell. Maskoption The following options are available by mask op- tion which must be selected prior to manufac- turing. · Each bit of input ports PS, PP with or without pull-highresistor. · Each bit of input ports PS, PP function as HALTinterrupttrigger. · Each bit of output port PA0~PA2 with CMOS oropendrainNMOS. · 8 bit programmable TIMER with internal fre- quency sources. There are 13 (the sixth stage is reserved for internal use) internal fre- quency sources which can be selected as clockingsignal. · Sixkindsofsoundclockfrequency: fSYS/2 m ,m=0,1,2,3,4,5 12345678123 4 VDD 4/5 VDD 3/5 VDD 2/5 VDD 1/5 VDD GND COM0 512Hz 64Hz 5 COM1 SEG0 VDD 4/5 VDD 3/5 VDD 2/5 VDD 1/5 VDD GND VDD 4/5 VDD 3/5 VDD 2/5 VDD 1/5 VDD GND D CK Q Q mask option internal bus VDD Outputport - PA0~PA2 VDD internal bus wake-up pull-high mask option read control wake-up mask option - |
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