ARM920T datasheet(13/350 Pages) ATMEL

13 / 350 page

List of Figures

ARM DDI 0151C

xiii

Figure 12-2

Two cycle load interlock .......................................................................................... 12-7

Figure 12-3

LDM interlock .......................................................................................................... 12-8

Figure 12-4

LDM dependent interlock ...................................................................................... 12-10

Figure 13-1

ARM920T FCLK timed coprocessor interface ......................................................... 13-2

Figure 13-2

ARM920T BCLK timed coprocessor interface ........................................................ 13-3

Figure 13-3

ARM920T FCLK related signal timing ..................................................................... 13-4

Figure 13-4

ARM920T BCLK related signal timing ..................................................................... 13-5

Figure 13-5

ARM920T SDOUTBS to TDO relationship .............................................................. 13-5

Figure 13-6

ARM920T nTRST to other signals relationship ....................................................... 13-6

Figure 13-7

ARM920T JTAG output signal timing ...................................................................... 13-7

Figure 13-8

ARM920T JTAG input signal timing ........................................................................ 13-8

Figure 13-9

ARM920T FCLK related debug output timing ......................................................... 13-8

Figure 13-10

ARM920T BCLK related debug output timing ......................................................... 13-9

Figure 13-11

ARM920T TCK related debug output timing ......................................................... 13-10

Figure 13-12

ARM920T EDBGRQ to DBGRQI relationship ....................................................... 13-10

Figure 13-13

ARM920T DBGEN to output relationship .............................................................. 13-11

Figure 13-14

ARM920T BCLK related Trace Interface Port timing ............................................ 13-11

Figure 13-15

ARM920T FCLK related Trace Interface Port timing ............................................. 13-12

Figure 13-16

ARM920T BnRES timing ....................................................................................... 13-12

Figure 13-17

ARM920T ASB slave transfer timing ..................................................................... 13-13

Figure 13-18

ARM920T ASB master transfer timing .................................................................. 13-14

Figure 13-19

ARM920T ASB master transfer timing .................................................................. 13-15

Figure B-1

CP15 MRC and MCR bit pattern ............................................................................... B-2

Figure B-2

Rd format, CAM read .............................................................................................. B-12

Figure B-3

Rd format, CAM write .............................................................................................. B-12

Figure B-4

Rd format, RAM read .............................................................................................. B-12

Figure B-5

Rd format, RAM write .............................................................................................. B-13

Figure B-6

Rd format, CAM match RAM read .......................................................................... B-13

Figure B-7

Data format, CAM read ........................................................................................... B-13

Figure B-8

Data format, RAM read ........................................................................................... B-13

Figure B-9

Data format, CAM match RAM read ....................................................................... B-14

Figure B-10

Rd format, write I or D cache victim and lockdown base ......................................... B-15

Figure B-11

Rd format, write I or D cache victim ........................................................................ B-15

Figure B-12

Rd format, CAM write and data format, CAM read .................................................. B-24

Figure B-13

Rd format, RAM1 write ............................................................................................ B-24

Figure B-14

Data format, RAM1 read ......................................................................................... B-25

Figure B-15

Rd format, RAM2 write and data format, RAM2 read .............................................. B-26

Figure B-16

Rd format, write I or D TLB lockdown ..................................................................... B-27

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