ARM920T datasheet(4/350 Pages) ATMEL

4 / 350 page

Contents

ARM DDI 0151C

3.8

External aborts ......................................................................................... 3-28

3.9

Interaction of the MMU and caches .......................................................... 3-29

Chapter 4

Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

4.1

About the caches and write buffer .............................................................. 4-2

4.2

ICache ........................................................................................................ 4-4

4.3

DCache and write buffer ............................................................................. 4-9

4.4

Cache coherence ..................................................................................... 4-17

4.5

Cache cleaning when lockdown is in use ................................................. 4-20

4.6

Implementation notes ............................................................................... 4-21

4.7

Physical address TAG RAM ..................................................................... 4-22

4.8

Drain write buffer ...................................................................................... 4-23

4.9

Wait for interrupt ....................................................................................... 4-24

Chapter 5

Clock Modes

5.1

About ARM920T clocking ........................................................................... 5-2

5.2

FastBus mode ............................................................................................ 5-3

5.3

Synchronous mode ..................................................................................... 5-4

5.4

Asynchronous mode ................................................................................... 5-6

Chapter 6

Bus Interface Unit

6.1

About the ARM920T bus interface ............................................................. 6-2

6.2

Unidirectional AMBA ASB interface ............................................................ 6-3

6.3

Fully-compliant AMBA ASB interface ......................................................... 6-5

6.4

AMBA AHB interface ................................................................................ 6-21

6.5

Level 2 cache support and performance analysis .................................... 6-23

Chapter 7

Coprocessor Interface

7.1

About the ARM920T coprocessor interface ................................................ 7-2

7.2

LDC/STC .................................................................................................... 7-5

7.3

MCR/MRC .................................................................................................. 7-9

7.4

Interlocked MCR ....................................................................................... 7-11

7.5

CDP .......................................................................................................... 7-13

7.6

Privileged instructions ............................................................................... 7-15

7.7

Busy-waiting and interrupts ...................................................................... 7-17

Chapter 8

Trace Interface Port

8.1

About the ETM interface ............................................................................. 8-2

Chapter 9

Debug Support

9.1

About debug ............................................................................................... 9-2

9.2

Debug systems ........................................................................................... 9-3

9.3

Debug interface signals .............................................................................. 9-5

9.4

Scan chains and JTAG interface .............................................................. 9-11

9.5

The JTAG state machine .......................................................................... 9-12

9.6

Test data registers .................................................................................... 9-19

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