ARM920T datasheet(5/350 Pages) ATMEL

5 / 350 page

Contents

ARM DDI 0151C

9.7

ARM920T core clocks ............................................................................... 9-42

9.8

Clock switching during debug ................................................................... 9-43

9.9

Clock switching during test ........................................................................ 9-44

9.10

Determining the core state and system state ............................................ 9-45

9.11

Exit from debug state ................................................................................ 9-48

9.12

The behavior of the program counter during debug .................................. 9-51

9.13

EmbeddedICE macrocell .......................................................................... 9-54

9.14

Vector catching ......................................................................................... 9-62

9.15

Single-stepping ......................................................................................... 9-63

9.16

Debug communications channel ............................................................... 9-64

Chapter 10

TrackingICE

10.1

About TrackingICE .................................................................................... 10-2

10.2

Timing requirements ................................................................................. 10-3

10.3

TrackingICE outputs ................................................................................. 10-4

Chapter 11

AMBA Test Interface

11.1

About the AMBA test interface .................................................................. 11-2

11.2

Entering and exiting AMBA Test ............................................................... 11-3

11.3

Functional test ........................................................................................... 11-4

11.4

Burst operations ...................................................................................... 11-11

11.5

PA TAG RAM test ................................................................................... 11-12

11.6

Cache test ............................................................................................... 11-15

11.7

MMU test ................................................................................................. 11-19

Chapter 12

Instruction Cycle Summary and Interlocks

12.1

About the instruction cycle summary ........................................................ 12-2

12.2

Instruction cycle times ............................................................................... 12-3

12.3

Interlocks ................................................................................................... 12-6

Chapter 13

AC Characteristics

13.1

ARM920T timing diagrams ........................................................................ 13-2

13.2

ARM920T timing parameters .................................................................. 13-16

13.3

Timing definitions for the ARM920T Trace Interface Port ....................... 13-26

Appendix A

Signal Descriptions

A.1

AMBA signals .............................................................................................. A-2

A.2

Coprocessor interface signals ..................................................................... A-5

A.3

JTAG and TAP controller signals ................................................................ A-7

A.4

Debug signals ........................................................................................... A-10

A.5

Miscellaneous signals ............................................................................... A-12

A.6

ARM920T Trace Interface Port signals ..................................................... A-13

Appendix B

CP15 Test Registers

B.1

About the test registers ............................................................................... B-2

B.2

Test state register ....................................................................................... B-3

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