IDT7M1001S40C datasheet(8/11 Pages) IDT

Il numero della parte	IDT7M1001S40C

Spiegazioni elettronici	128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

PDF	11 Pages

Scroll/Zoom	100%

Produttore elettronici	IDT [Integrated Device Technology]

Homepage	http://www.idt.com

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8 / 11 page

7.5

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)

NOTE:

CS = HIGH for the duration of the above timing (both write and read cycle).

2804 drw 10

2804 drw 11

NOTES:

1. D0R = D0L = LOW, L_

CS = R_CS = HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.

2. "A" may be either left or right port. "B" is the opposite port from "A".

3. This parameter is measured from R/

WA or SEMA going HIGH to R/WB or SEMB going HIGH.

4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

t AW

t WR

t ACS

t AA

t OH

t WP

t SOP

t DW

t AS

t WP

t DH

t SWRD

t OE

t SOP

VALID ADDRESS

DATA IN

VALID

DATAOUT

VALID

READ CYCLE

WRITE CYCLE

A 0 - A2

SEM

DATA 0

R/W

TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)

MATCH

t SPS

A 0A - A 2A

R/W

SEM

A 0B - A 2B

R/W

SEM

SIDE

(2)

“A”

SIDE

(2)

“B”

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