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M80C86 Scheda tecnica(PDF) 8 Page - Intel Corporation |
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M80C86 Scheda tecnica(HTML) 8 Page - Intel Corporation |
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8 / 19 page ![]() M80C86M80C86-2 WORKAROUND A hardware workaround has been designed and tested The workaround circuit (Figure 3) qualifies the RD signal coming out of the M80C8680C88 during valid read cycles and forces it to be inactive otherwise (see the timing diagram in Figure 4) The- delay in the RDM signal is limited to 6 ns (Max) by using fast gate devices This should not have any impact in the design since the RDM pulse width is still the same as the orginal RD pulse width RDM is also guaranteed to go inactive during the T4 state of all read cycles 271058 – 18 Figure 3 271058 – 19 Figure 4 8 |
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