M80C86 datasheet(5/19 Pages) INTEL

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M80C86M80C86-2

Table 1 Pin Description

(Continued)

Symbol

Pin No

Type

Name and Function

If the local bus is idle when the request is made the two possible

events will follow

1 Local bus will be released during the next clock

2 A memory cycle will start within 3 clocks Now the four rules for a

currently active memory cycle apply with condition number 1 already

satisfied

LOCK

output indicates that other system bus masters are not to gain

control of the system bus while LOCK is active LOW The LOCK

signal is activated by the ‘‘LOCK’’ prefix instruction and remains

active until the completion of the next instruction This signal is active

LOW and floats to 3-state OFF(1) in ‘‘hold acknowledge’’

QS1 QS0

24 25

QUEUE STATUS

The queue status is valid during the CLK cycle

after which the queue operation is performed

QS1 and QS0 provide status to allow external tracking of the internal

M80C86 instruction queue

QS1

QS0

Characteristics

0 (LOW)

No Operation

First Byte of Op Code from Queue

1 (HIGH)

Empty the Queue

Subsequent Byte from Queue

The following pin function descriptions are for the M80C86 in minimum mode (ie MNMX eVCC ) Only the

pin functions which are unique to minimum mode are described all other pin functions are described above

MIO

STATUS LINE

logically equivalent to S2 in the maximum mode It

is used to distinguish a memory access from an IO access MIO

becomes valid in the T4 preceding a bus cycle and remains valid

until the final T4 of the cycle (MeHIGH IOeLOW) MIO floats to

3-state OFF(1) in local bus ‘‘hold acknowledge’’

WRITE

indicates that the processor is performing a write memory

or write IO cycle depending on the state of the MIO signal WR is

active for T2 T3 and TW of any write cycle It is active LOW and

floats to 3-state OFF(1) in local bus ‘‘hold acknowledge’’

INTA

INTA is used as a read strobe for interrupt acknowledge cycles It is

active LOW during T2 T3 and TW of each interrupt acknowledge

cycle

ALE

ADDRESS LATCH ENABLE

provided by the processor to latch

the address into an address latch It is a HIGH pulse active during

T1 of any bus cycle Note that ALE is never floated

DTR

DATA TRANSMITRECEIVE

needed in minimum system that

desires to use a data bus transceiver It is used to control the

direction of data flow through the transceiver Logically DTR is

equivalent to S1 in the maximum mode and its timing is the same

as for MIO (TeHIGH ReLOW) This signal floats to 3-state

OFF(1) in local bus ‘‘hold acknowledge’’

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