M80C86M80C86-2

Timing Responses

Symbol

Parameter

M80C86

M80C86-2

Units

Comments

Min

Max

Min

Max

TCLAV

Address Valid Delay

10

110

10

60

ns

TCLAX

Address Hold Time

10

10

ns

TCLAZ

Address Float

TCLAX

80

TCLAX

50

ns

Delay

TLHLL

ALE Width

TCLCHb20

TCLCHb10

ns

TCLLH

ALE Active Delay

80

50

ns

TCHLL

ALE Inactive Delay

85

55

ns

TLLAX

Address Hold Time

TCHCLb10

TCHCLb10

ns

to ALE Inactive

TCLDV

Data Valid Delay

10

110

10

60

ns

TCHDX

Data Hold Time

10

10

ns

TWHDX

Data Hold Time

TCLCHb30

TCLCHb30

ns

After WR

TCVCTV

Control Active

10

110

10

70

ns

Delay 1

TCHCTV

Control Active

10

110

10

60

ns

Delay 2

TCVCTX

Control Inactive

10

110

10

70

ns

Delay

TAZRL

Address Float to

0

0

ns

READ Active

TCLRL

RD Active Delay

10

165

10

100

ns

TCLRH

RD Inactive Delay

10

150

10

80

ns

TRHAV

RD Inactive to Next

TCLCLb45

TCLCLb40

ns

Address Active

TCLHAV

HLDA Valid Delay

10

160

10

100

ns

TRLRH

RD Width

2TCLCLb75

2TCLCLb50

ns

TWLWH

WR Width

2TCLCLb60

2TCLCLb40

ns

TAVAL

Address Valid to

TCLCHb60

TCLCHb40

ns

ALE Low

TOLOH

Output Rise Time

15

15

ns

From 08V to 20V

TOHOL

Output Fall Time

15

15

ns

From 20V to 08V

NOTES

1 Signal at M82C84A shown for reference only See M82C84A data sheet for the most recent specifications

2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK

3 Applies only to T2 state (5 ns into T3)

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