AN1625 APPLICATION NOTE

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rent reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage is ob-

served between two OUT pins when a phase change turns a high-side off during an off-time, and this must

always be kept below 60 V [2].

Figure 3. Currents and voltages if a phase change turns a high-side off during off-time.

Figure 4 shows the voltage waveforms at the OUT pins referring to a possible practical situation, with a peak

ground spike amplitude is -2.64 V for one output; the other OUT pin is at about 55 V. In these conditions, total

differential voltage reaches almost 60 V, which is the absolute maximum rating for the DMOS. Keeping differ-

ential voltage between two Output pins within rated values is a must that can be accomplished with proper se-

lection of Bulk capacitor value and equivalent series resistance (ESR), according to current peaks and adopting

good layout practices to minimize PCB parasitic inductances (see below) [2].

Figure 4. Voltage at the two outputs if a phase change turns a high-side off during off-time.

on-time

off-time

during off-time

a phase change can occur

PCB Parasitic

Inductance

R

Bulk

Capacitor

Equivalent

Circuit

ESR

ESL

PCB Parasitic

Inductance

Current starts

flowing in the

third half bridge

OUT1

OUT2

SENSE