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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AN2847 Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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AN2847 Scheda tecnica(HTML) 10 Page - STMicroelectronics |
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10 / 31 page  Start-up sequence AN2847 10/31 Doc ID 15136 Rev 2 2.3 Data ready vs. interrupt signal The device has two pins which can be activated to generate either the data-ready signal or the interrupt signal. The functionality of the pins is selected acting on bit I1(2)_CFGx bits of the CTRL_REG3 register, according to Table 4 and the block diagram shown in Figure 2. Figure 2. Interrupt and DataReady signal generation block diagram In particular, the data-ready (DR) signal rises to 1 when a new set of acceleration data has been generated and is available for reading. The signal is reset after all the enabled channels are read through the serial interface. T1 Reading period T0-T2 T2 New data generation 616 µs Table 3. Timing value to prevent data loss Time Description Typ Table 4. Data signal on INT 1 and INT 2 pads I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pin 0 0 Interrupt 1 (2) source 0 1 Interrupt 1 source OR Interrupt 2 source 1 0 Data ready 1 1 Boot running |
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