AN2842

List of figures

Doc ID 15110 Rev 1

3/22

List of figures

Figure 1.

Two MOSFETs connected in parallel with a single boost inductor . . . . . . . . . . . . . . . . . . . . 4

Figure 2.

Two MOSFETs connected in parallel with a different boost inductor . . . . . . . . . . . . . . . . . . 4

Figure 3.

Three MOSFETs connected in parallel with a single boost inductor . . . . . . . . . . . . . . . . . . 4

Figure 4.

Parasitic inductance in a circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5.

Details of current imbalance during turn-on due to external parasitic inductances . . . . . . . 6

Figure 6.

Details of current imbalance during steady state operation due to the layout . . . . . . . . . . . 7

Figure 7.

Current imbalance due to layout during steady state operation when the device

position is changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8.

Details of current balance when circuit has very similar parameters . . . . . . . . . . . . . . . . . . 8

Figure 9.

Details of current imbalance during turn-on due principally at the voltage on

the gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.

Details of current imbalance during turn-on when the voltage on the gate

circuitry is very comparable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 11.

Details of current imbalance during turn-off due principally to the voltage

on the gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12.

Details of current imbalance during turn-off when the voltage on the gate

circuitry is very comparable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 13.

Contribution of the current spike value during the turn-on phase . . . . . . . . . . . . . . . . . . . . 11

Figure 14.

Current spike during the turn-on phase when a fast diode is used. . . . . . . . . . . . . . . . . . . 12

Figure 15.

Current spike during the turn-on phase when an ultra fast diode is used. . . . . . . . . . . . . . 12

Figure 16.

Instant of failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 17.

Schematics of two devices connected in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.

Figure 19.

Figure 20.

Details of current imbalance due to a difference in RDS(on) value . . . . . . . . . . . . . . . . . . . 17

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Details of current imbalance during turn-on with high gfs spread . . . . . . . . . . . . . . . . . . . . 19