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Guidelines for connecting via JTAG protocol to the STR71x microcontroller

– The ICE debug control comms register is read (via scan chain2). This register is read in order

to determine whether the processor or the debugger can write to this register to initiate the

handshaking DBGRQ/DBGACK.

– The ICE debug status register is read to check DBGACK . This is to make sure the core is

not already halted in debug mode.

– DBGACK is set to 1, the system is in debug mode.

– The first instructions are passed to the core via scan chain 1 in debug mode.

– DBGACK is deasserted by writing to the ICE debug control register.

– Read back DBGACK = 0 from the ICE debug status register.

– NJTRST and SYSNRST are asserted, TAP is in RESTART (exit from debug mode).

– SYSNRST is deasserted.

4.2 CONNECTION HANDSHAKE PROTOCOL

This sequence is mandatory for connecting to the STR71x. This section could be executed

after the 2048TCK periods as described in Figure 2. The connection sequence:

– The debugger halts the CPU by asserting DBGRQ internally and waits for DBGACK signal

from the CPU.

– Instructions and data are passed to the core via the Embedded ICE scan chain 1, and the

DBGRQ/DBGACK protocol is controlled via scan chain 2.

– TAP goes to soft reset (TMS=1 for 5 TCK pulses) to make sure the JTAG connection starts

from a reset state

– *Scan chain 2 (to access ICE register) is selected to write to the ICE debug control register:

DBGRQ is asserted to the CPU in order to put the CPU in debug mode. Then the ICE debug

status register is read in a loop until DGBACK is asserted by the CPU. A TAP soft reset is

performed in every loop iteration.

– The status register is read, and DBGACK is asserted, the core has entered debug state. As

described in Section 2.3, the CPU enters Halt mode.

– Once in debug state, the CPU needs to be isolated from the rest of the system so that the

debugger is in full control. System peripherals need to be aware that the core is in debug

state, the core is clocked by DCK instead of MCLK, and all the interrupts to the core are dis-

abled. This is done by forcing bit 0 and bit 2 to logic 1 (DGBACK and INT) in the ICE debug

control register, and reading back the ICE status register to make sure these signals have

been asserted.

– The core In debug state shifts instructions/data using scan chain 1 from which point we can

execute instructions to the core, read/write register values in debug state.