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Guidelines for connecting via JTAG protocol to the STR71x microcontroller

Figure 2. STR71x Reset Sequence

The reset sequence is divided into 6 phases:

1.

STR71x RESET: The whole device is under reset.

2.

CLOCK STABILIZATION: The CPU and the flash are kept under reset for the internal

clock stabilization.

3&4.

FLASH INITIALIZATION: The flash is initialized internally keeping the CPU under

reset.

This period varies as it is clocked by an embedded RC oscillator. The 2048TCK

5.

CLOCK START-UP: MCLK is supplied to the various internal blocks of the device

while CPU and peripherals are kept under reset.

6.

USER APPLICATION EXECUTION: The user application is executed from address

0x00000000 by the CPU.

3.3 STANDBY PROGRAM

To illustrate the connection sequence in Standby mode, we can use a piece of code, which we

call the Standby program, that puts the core in Standby by setting the PWRDWN bit in the

power control register of the PRCCU. We place this code in internal Flash for execution. This

is the worst case scenario for the debugger connecting to the target since once the CPU starts

to execute the code at address 0x0, the core enters Standby mode.

Therefore this is a perfect test for the JTAG connection sequence since the only way to con-

nect from Standby is to perform a system reset, then after the flash initialization phase (phase

CK

RSTIN

JTAG_EN

RSTARM

MCLK

PHASE

~20µs

2

3

456

1