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Guidelines for connecting via JTAG protocol to the STR71x microcontroller

1 OVERVIEW

One of the features of the STR71x is to allow the user to boot an application from internal

RAM, which could be used for debugging purposes. However, that system configuration may

potentially result in a hang-up when the debugger attempts to initiate the JTAG communica-

tion with the microcontroller. This could be caused by some random code in RAM that could

set the STR71x in an unpredictable mode and prevent JTAG connection to the target.

Section 2 of this application note describes the inherent features of the STR71x affecting the

JTAG connection. Section 3 presents a set of solutions for overcoming all the connection is-

sues. Finally, Section 4, gives a detailed description of the JTAG connection sequence from

the point of view of the JTAG protocol converter.

2 PARAMETERS AFFECTING JTAG CONNECTION

This section covers all the known parameters that affect the JTAG connection.

2.1 DELAY FOR FLASH INITIALIZATION

One aspect to be taken into account is the time for the internal STR71x flash initialization fol-

lowing a system reset. The flash initialization holds an internal signal controlling the ARM

JTAG Reset pin in an undefined state for a deterministic amount of time. This is explained in

detail in section 3.2.

2.2 RESET SIGNALS CONNECTED

Having both system reset and the JTAG reset connected to the same signal will prevent con-

nection since the system reset has to be asserted during the JTAG communication protocol

and released before the start of the application. Therefore having both pins tied to the same

signal will prevent any JTAG communication with the embedded ICE registers.

2.3 PUTTING THE STR71x CPU IN HALT MODE

The Halt Mode of the STR71x CPU is used for debug purposes. This means that once debug

state is initiated, the core is stopped and isolated from the rest of the system until the de-

bugger restores the system state.

The STR71x can only switch to debug state by switching from the main CPU clock (MCLK) to

the ARM JTAG clock (DCLK) controlled by the debugger. The STR71x CPU enters Halt mode

on the next falling edge of MCLK after DBGRQ is asserted. Therefore MCLK has to be running

internally to be able to connect via JTAG. For this reason, it is not possible to connect via

JTAG when the STR71x is in WFI (Wait For Interrupt) mode or STOP mode.