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Main differences between STM32F packages and their possible modifications

AN3307

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Doc ID 18186 Rev 4

Main differences between STM32F packages

and their possible modifications

This document describes mainly the basic STM32F1xx package; as the other packages are

its derivatives. Users can find some slight differences mainly due to the hardware deviations,

compilers and debugging tools incompatibilities. Main differences are focused on in this

section. The user can find a complete list and detailed information about STL files included

in documentation *.chm file, which is extracted and attached for each package.

CPU Tests

STM32F3xx package. With the STM32F0xx package, all the instructions in the tests loading

immediate 32-bit constant operands are replaced by instructions loading constants placed

at code memory, due to restricted instruction set of ARM Cortex™-M0 core.

Clock tests and time base interval measurement

Instead of Real-time Clock (RTC) counter used in the STM32F1xx package, a sub-second

different implementation of RTC registers. The clock system measurement technique differs

slightly due to this fact, in these packages. Internal timers are used for cross-check

frequency measurement when this feature is available mainly to determine harmonic or

sub-harmonic frequencies if the system clock is provided by the external crystal.

SRAM tests

Some ST microcontrollers feature a built-in word protection with single bit redundancy

(hardware parity check) applied on CCM RAM or on part of SRAM, at least. This hardware

protection is one of the acceptable methods required by the IEC 60335 and IEC 60730

Class B standards. It reduces software testing overhead significantly. The applied software

SRAM March test can be removed from both startup and runtime test sets in this case. It

can be used optionally for testing the parts of RAM which are not covered by the hardware

parity check, or as a supplementary testing method. The diagnostic coverage of single bit

redundancy protection is limited to detect specific range of errors; so additional checks can

be required by the certification authority at some safety critical cases. An example could be

a combination of hardware parity protection and software March test which can be an

acceptable test of variable memory satisfying even more severe Class C criteria. The

reliability of hardware parity check can be increased, too, by other suitable methods like

using double inverse storage of safety critical information at physically separated areas (e.g.

to prevent a corruption caused by radiation or EMI which typically attacks a limited physical

memory locality).

The hardware parity check is an optional feature. When it is enabled, an unintentional parity

error event can be detected during execution of startup self-test procedure due to not

initialized parity system (e.g. case of local variables if they are allocated and read out while

using different data access to memory).

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