LT1186FC datasheet(12/16 Pages) LINER

12 / 16 page

LT1186F

APPLICATIONS INFORMATION

circuitry provides a ratio of switch current to driver current

of about 50:1.

8-Bit Current Output DAC

The 8-bit current output DAC is guaranteed monotonic and

is digitally adjustable by the 8-bit counter in 256 equal

steps. On power up, the counter resets to 80H and the DAC

assumes its mid-range value. The current output IOUT

drives the ICCFL pin and sets control current for the lamp

current programming block. The DAC has its own 1.24V

bandgap reference and a voltage to current converter that

is trimmed at wafer sort to provide the precision full-scale

current reference. Over temperature, the current output of

the DAC is 50

µA ±6%.

Digital Interface

On power-up, a logic high at CS configures the DAC into

pulse mode. If CS is ever pulled low, the chip configures

into SPI mode until VCC resets. On power-up in pulse

mode, a logic high at DIN puts the counter into increment-

only mode. If UP/DN (DIN) is ever pulled low, the counter

configures into increment/decrement mode until VCC re-

sets. These modes are illustrated in Figure 1.

SINGLE DAC

SPI MODE

PULSE MODE

LT1186F • F01a

INCREMENT/

DECREMENT

INCREMENT-

ONLY

CS STAYS

HIGH

CS EVER

GOES LOW

DIN (UP/DN)

EVER GOES

LOW

DIN STAYS

HIGH

Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)

Figure 1b. SPI Mode Setup

POWER ON

VCC

LT1186F • F01b

CS EVER GOES LOW

POWER ON

VCC

LT1186F • F01c

CS ALWAYS HIGH

DIN ALWAYS HIGH

Figure 1c. Pulse Mode Setup (Increment Only)

POWER ON

VCC

CS ALWAYS HIGH

LT1186F • F01d

UP/DN

UP/DN EVER GOES LOW

Figure 1d. Pulse Mode Setup (Increment/Decrement)

Standard SPI Mode

Refer to the serial interface operating sequence in Figure

2. A falling edge at CS initiates the data transfer. After the

falling CS is recognized, DOUT comes out of three-state.

The clock (CLK) synchronizes the data transfer. Each input

bit shifts into DIN beginning with the MSB on the rising CLK

edge and each previous data bit shifts out of DOUT begin-

ning with the MSB on the falling CLK edge. After the 8-bit

serial input data is shifted in, a rising edge at CS transfers

the data into the counter, the DAC assumes the new value

IOUT = (8-bit serial input data)(50µA)/255 and the DOUT pin

returns to a high impedance state.

1-Wire Interface (Pulse Mode)

In increment-only pulse mode, each rising edge of CLK

increments the upper six bits of the counter by one count.

When incremented beyond 11111100B, the counter rolls

over and sets the DAC to the minimum value 00000000B.

Therefore, a single pulse applied to CLK increases the

upper 6-bit counter by one-step, and 63 pulse applied to

CLK decreases the counter by one-step. The last two LSBs

are always zero in this mode. IOUT = (B7B6B5B4B3B2B1B0)

(50

µA)/255. The upper 6-bit counter = B7B6B5B4B3B2and

B1 = B0 = 0. To configure the LT1186F into increment-only

mode, tie CS and DIN to VCC.

LT1186FC Scheda tecnica(PDF) 12 Page - Linear Technology

LT1186FC Scheda tecnica(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL