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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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LT1186FC Scheda tecnica(PDF) 3 Page - Linear Technology |
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LT1186FC Scheda tecnica(HTML) 3 Page - Linear Technology |
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3 / 16 page  3 LT1186F TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT = CLK = GND, CCFL VC = 0.5V, unless otherwise specified. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT CCFL High-Side Sense Servo Current ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V q 0.93 1.00 1.07 A TJ < 0°C q 0.91 1.00 1.07 A CCFL High-Side Sense Servo Current BAT = 5V to 30V, ICCFL = 100µA, 0.1 0.16 %/V Line Regulation I(VC) = 0µA at CCFL VC = 1.5V CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins q 50 100 150 µA BULB Protect Servo Voltage ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V, q 6.5 7.0 7.5 V Servo Voltage Measured between BAT and BULB Pins BULB Input Bias Current ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V 5 9 µA ILIM CCFL Switch Current Limit Duty Cycle = 50% q 1.25 1.9 3.0 A Duty Cycle = 75% (Note 3) q 0.9 1.6 2.6 A VSAT CCFL Switch On Resistance CCFL ISW = 1A q 0.6 1.0 Ω ∆I Q Supply Current Increase During CCFL ISW = 1A 20 30 mA/A ∆ISW CCFL Switch On Time DAC Resolution 8 Bits DAC Full-Scale Current V(IOUT) = 0.465V, Measured in SPI Mode 48.5 50 51.5 µA q 47.0 50 53.0 µA DAC Zero Scale Current V(IOUT) = 0.465V, Measured in SPI Mode 200 nA DAC Differential Nonlinearity q ±2.0 LSB DAC Supply Voltage Rejection 3V ≤ VCC ≤ 6.5V, IOUT = Full Scale, V(IOUT) = 0.465V q 24 LSB Logic Input Current 0V ≤ VIN ≤ VCC q ±1 µA VIH High Level Input Voltage VCC = 3.3V q 1.9 V VCC = 5V q 2V VIL Low Level Input Voltage VCC = 3.3V q 0.45 V VCC = 5V q 0.80 V VOH High Level Output Voltage VCC = 3.3V, IO = 400µA q 2.1 V VCC = 5V, IO = 400µA q 2.4 V VOL Low Level Output Voltage VCC = 3.3V, IO = 1mA q 0.4 V VCC = 5V, IO = 2mA q 0.4 V IOZ Three-State Output Leakage VCS = VCC q ±5 µA SERIAL INTERFACE (Notes 4, 5) fCLK Clock Frequency q 2 MHz tCKS Setup Time, CLK ↓ Before CS↓ q 150 ns tCSS Setup Time, CS ↓ Before CLK↑ q 400 ns tDV CS ↓ to DOUT Valid See Test Circuits q 150 ns tDS Data in Setup Time Before CLK ↑ q 150 ns tDH Data in Hold Time After CLK ↑ q 150 ns tDO CLK ↓ to DOUT Valid See Test Circuits q 150 ns tCKHI CLK High Time q 200 ns tCKLO CLK Low Time q 250 ns tCSH CLK ↓ Before CS↑ q 150 ns tDZ CS ↑ to DOUT In Hi-Z See Test Circuits q 400 ns tCKH CS ↑Before CLK↑ q 400 ns |
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