1

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01

©2001, Micron Technology, Inc.

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.

Architecture

64 Meg x 4

32 Meg x 8

16 Meg x 16

Configuration

16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks

RefreshCount

8K

8K

8K

RowAddressing

8K (A0–A12)

8K (A0–A12)

8K (A0–A12)

BankAddressing

4(BA0,BA1)

4(BA0,BA1)

4(BA0,BA1)

ColumnAddressing

2K (A0–A9, A11)

1K (A0–A9)

512 (A0– A8)

DOUBLE DATA RATE

(DDR) SDRAM

MT46V64M4 – 16 Meg x 4 x 4 banks

MT46V32M8 – 8 Meg x 8 x 4 banks

MT46V16M16 – 4 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/dramds

FEATURES

• 167 MHz Clock, 333 Mb/s/p data rate

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (x16 has two - one per byte)

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has

two - one per byte)

• Programmable burst lengths: 2, 4, or 8

• Concurrent Auto Precharge option supported

• Auto Refresh and Self Refresh Modes

• FBGA package available

• 2.5V I/O (SSTL_2 compatible)

• Backwards compatible with DDR200 and DDR266

OPTIONS

PART NUMBER

• Configuration

64 Meg x 4 (16 Meg x 4 x 4 banks)

64M4

32 Meg x 8 (8 Meg x 8 x 4 banks)

32M8

16 Meg x 16 (4 Meg x 16 x 4 banks)

16M16

• Plastic Package

66-Pin TSOP (OCPL)

T G

60-Ball FBGA (16x9mm)

FJ

• Timing - Cycle Time

-6

-6T

-75Z

• Self Refresh

Standard

none

NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing

2. Supports PC2100 modules with 2-3-3 timing

CONFIGURATION

DDR333 COMPATIBILITY

DDR333 meets or surpasses all DDR266 timing re-

quirements thus assuring full backwards compatibility

with current DDR designs. In addition, these devices

for improved timing performance.

The 256Mb,

odic refresh interval of 7.8us.

The standard 66-pin TSOP package is offered for

point-to-point applications where the FBGA package

is intended for the multi-drop systems.

The Micron 256Mb data sheet provides full specifi-

cations and functionality unless specified herein.

SPEED

CLOCK RATE

DATA-OUT

ACCESS DQS-DQ

GRADE

SKEW

-6

133 MHz

167 MHz

2.15ns

±0.70ns

+0.35ns

-6T

133 MHz

167 MHz

2.0ns

±0.75ns

+0.45ns

-75Z

133 MHz

133 MHz

2.5ns

±0.75ns

+0.50ns

NOTE:

1. CL = CAS (Read) Latency

2. With a 50/50 clock duty cycle and a minimum clock

rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).

3. -75, -8 are also available; see base data sheet.