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AS5047P Scheda tecnica(PDF) 12 Page - ams AG |
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AS5047P Scheda tecnica(HTML) 12 Page - ams AG |
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12 / 40 page ![]() Page 12 ams Datasheet Document Feedback [v1-00] 2014-Oct-31 AS5047P − Detailed Description Figure 12: SPI Timing SPI Transaction An SPI transaction consists of a 16-bit command frame followed by a 16-bit data frame. Figure 13 shows the structure of the command frame. Figure 13: SPI Command Frame To increase the reliability of communication over the SPI, an even parity bit PARC must be generated and sent. A wrong setting of the parity bit causes the PARERR bit in the error flag register to be set. The parity bit is calculated from the 16-bit command frame. The 16-bit command specifies whether the transaction is a read or a write and the address. Parameter Description Min Max Units tL Time between CSn falling edge and CLK rising edge 350 ns tclk Serial clock period 100 ns tclkL Low period of serial clock 50 ns tclkH High period of serial clock 50 ns tH Time between last falling edge of CLK and rising edge of CSn tclk / 2 ns tCSn High time of CSn between two transmissions 350 ns tMOSI Data input valid to falling clock edge 20 ns tMISO CLK edge to data output valid 51 ns tOZ Release bus time after CS rising edge. 10 ns Bit Name Description 15 PARC Parity bit (even) calculated on the command frame 14 R/W 0: Write 1: Read 13:0 ADDR Address to read or write |
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