UPD1002 datasheet(20/46 Pages) MICROCHIP

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UPD1002

DS00001760B-page 20

 2014 Microchip Technology Inc.

SPI ROM Data

Out

SPI_ROM_DO

(PD)

SPI ROM data out

Note:

This signal must be pulled-up to VDDIO with

an external 10 k

Ω resistor for proper opera-

tion.

Power/Ground

VTR Supply

Input

VTR

+3.3 to +5.0 V main power supply input. This signal must

be connected to a 2.2 µF capacitor to ground. Refer to

Figure 2-6 for additional power connection information.

+3.3 to +5.0 V

Variable Volt-

age I/O Power

VDDIO

+3.3 V to +5.0 V variable I/O power supply input. Refer to

Figure 2-6 for additional power connection information.

Note:

When using internal +3.3 V regulator, these

pins must be externally connected to

VDD33_CAP.

+5.0 V VBUS

Input

VBUS

+5.0 V VBUS input. This signal provides power in the

dead battery case. This signal must be connected to a

2.2 µF capacitor to ground. Refer to Figure 2-6 for addi-

tional power connection information.

+1.8V Power

Delivery

PD_VDD18

+1.8 V power for Power Delivery PHY. Refer to Figure 2-6

for additional power connection information.

Note:

This pin must be connected to VDD18_CAP

pin externally when using the internal VDD18

regulator.

+1.8 V Power

Capacitance

VDD18_CAP

This pin is used to provide capacitance for the integrated

+1.8 V regulator and must be connected to a 1 µF

(<100 m

Ω ESR) capacitor to ground. Refer to Figure 2-6

for additional power connection information.

+1.8 V Analog

Power

Capacitance

VDD18A_CAP

This pin is used to provide capacitance for the integrated

+1.8 V analog regulator and must be connected to a 1 µF

(<100 m

Ω ESR) capacitor to ground. Refer to Figure 2-6

for additional power connection information.

+3.3 V Power

Capacitance

VDD33_CAP

+3.3 V regulator output. This pin must be connected to a

1µF (<100m

Ω ESR) capacitor to ground. Refer to

Figure 2-6 for additional power connection information.

Integrated

Power Switch

Capacitance

VSW_CAP

This pin is used to provide capacitance for the integrated

power switch and must be connected to a 1 µF (<100 m

ESR) capacitor to ground. Refer to Figure 2-6 for addi-

tional power connection information.

Ground

VSS

Common ground. This exposed pad must be connected

to the ground plane with a via array.

TABLE 2-2:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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