TC1775 datasheet(62/101 Pages) INFINEON

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TC1775

Data Sheet

V1.2, 2002-05

Preliminary

Clock Generation Unit

The Clock Generation Unit (CGU) in the TC1775, shown in Figure 18, consists of an

oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency

external clock signal to a high-speed internal clock for maximum performance. The PLL

also has fail-safe logic that detects degenerate external clock behavior such as abnormal

frequency deviations or a total loss of the external clock. It can execute emergency

actions if it looses its lock on the external clock.

In general, the CGU is controlled through the System Control Unit (SCU) module of the

TC1775.

Figure 18

Clock Generation Unit Block Diagram

Besides the two XTAL pins for the oscillator, input pins CLKSEL[2:0] and BYPASS are

used for configuration of the clock generation unit. These inputs are checked by the SCU

which generates the appropriate control signals and latches the state of these signals

into register PLL_CLC.

MCA04713

Oscillator

Circuit

XTAL1

XTAL2

OSC

Phase

Detect.

VCO

Divider

PLL

VCO

Divider

SYS

System_

CLK

Lock

Detector

OSC_OK

PLL

Locked

Deep

Sleep

NDIV[2:0]

VCO_

BYPASS

KDIV[2:0] PLL_

BYPASS

CLKSEL[2:0]

BYPASS

MUX

Clock Generation Unit

CGU

System Control Unit

SCU

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