TC1775 datasheet(21/101 Pages) INFINEON

21 / 101 page

TC1775

Data Sheet

V1.2, 2002-05

Preliminary

BYPASS

W22

PLL Bypass Control Input

BYPASS is used for direct drive mode operation of the clock

circuitry. This pin is sampled during power-on reset

(PORST = low). Its level is latched into the PLL Clock

Control Register PLL_CLC. The combination BYPASS = 1

and CLKSEL[2:0] = 000B during power-on reset is reserved.

CFG0

CFG1

CFG2

CFG3

Y23

Y22

W21

W23

Operation Configuration Inputs

The configuration inputs define the boot options of the

TC1775 after a hardware reset operation.

TRST3)

AA19

JTAG Module Reset/Enable Input

A low level at this pin resets and disables the JTAG module.

A high level enables the JTAG module.

TCK3)

AB19

JTAG Module Clock Input

TDI4)

AC19

JTAG Module Serial Data Input

TDO

AA18

JTAG Module Serial Data Output

TMS4)

AB20

JTAG Module State Machine Control Input

OCDSE4)

Y19

OCDS Enable Input

A low level on this pin during power-on reset (PORST =low)

enables the on-chip debug support (OCDS). In addition, the

level of this pin during power-on reset determines the boot

configuration.

BRKIN4)

AC20

OCDS Break Input

A low level on this pin causes a break in the chip’s execution

when the OCDS is enabled. In addition, the level of this pin

during power-on reset determines the boot configuration.

BRKOUT

AC18

OCDS Break Output

A low level on this pin indicates that a programmable OCDS

event has occurred.

NMI4)

Y20

Non-Maskable Interrupt Input

A high-to-low transition on this pin causes a NMI-Trap

request to the CPU.

Table 1

Pin Definitions and Functions (cont’d)

Symbol

Out

Functions

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