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IS43DR16640C Scheda tecnica(PDF) 18 Page - Integrated Silicon Solution, Inc |
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IS43DR16640C Scheda tecnica(HTML) 18 Page - Integrated Silicon Solution, Inc |
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18 / 49 page ![]() 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00A 6/4/2013 IS43/46DR81280C, IS43/46DR16640C Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) cont'd (For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.) Parameter Symbol DDR2-400 DDR2-533 Units Notes Min. Max. Min. Max. Active to active command period tRRD x8 7.5 – 7.5 – ns 4 x16 10 – 10 – Four Activate Window tFAW x8 37.5 – 37.5 – ns x16 50 – 50 – ns CAS to CAS command delay tCCD 2 – 2 – tCK Write recovery time tWR 15 – 15 – ns Auto precharge write recovery + precharge time tDAL WR + tRP – WR + tRP – tCK 14 Internal write to read command delay tWTR 10 – 7.5 – ns 24 Internal read to precharge command delay tRTP 7.5 – 7.5 – ns 3 CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 – 3 – tCK 27 Exit self refresh to a non-read command tXSNR tRFC + 10 – tRFC + 10 – ns Exit self refresh to a read command tXSRD 200 – 200 – tCK Exit precharge power down to any non- read command tXP 2 – 2 – tCK Exit active power down to read command tXARD 2 – 2 – tCK 1 Exit active power down to read command (slow exit, lower power) tXARDS 6 - AL – 6 - AL – tCK 1,2 ODT turn-on delay tAOND 2 2 2 2 tCK 16 ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC (max)+1 ns 16 ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2 x tCK + tAC(max)+1 tAC(min) + 2 2 x tCK + tAC(max)+1 ns ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK 17, 44 ODT turn-off tAOF tAC(min) tAC(max) + 0.6 tAC(min) tAC(max) + 0.6 ns 17, 44 ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5 x tCK + tAC(max)+1 tAC(min)+2 2.5 x tCK+ tAC(max)+1 ns ODT to power down entry latency tANPD 3 – 3 – tCK ODT power down exit latency tAXPD 8 – 8 – tCK Mode register set command cycle time tMRD 2 – 2 – tCK MRS command to ODT update delay tMOD 0 12 0 12 ns OCD drive mode output delay tOIT 0 12 0 12 ns Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK+tIH – tIS+tCK+tIH – ns 15 |
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