IS43DR16640C datasheet(21/49 Pages) ISSI

21 / 49 page

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00A

6/4/2013

IS43/46DR81280C, IS43/46DR16640C

Guidelines for AC Parameters

1. DDR2 SDRAM AC Timing Reference Load

Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing

parameters of the part. It is not intended to be either a precise representation of the typical system environment or

a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation

tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test

conditions (generally a coaxial transmission line terminated at the tester electronics).

VDDQ

DUT

DQS

RDQS

Output

VTT = VDDQ/2

Ω

Timing

reference

point

Figure - AC Timing Reference Load

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing

reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)

signal.

2. Slew Rate Measurement Levels

a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single

ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV

and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc)

to VIL(ac),max for falling edges.

For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = +

500 mV (+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between

DQS and DQS for differential strobe.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown in Figure "Slew Rate Test Load".

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of

the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method

by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships

are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing

VDDQ

DUT

RDQS, RDQS

S, DQS

Output

VTT = VDDQ/2

Ω

Test point

Figure - Slew Rate Test Load

relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing

methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via

the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure

proper operation.

IS43DR16640C Scheda tecnica(PDF) 21 Page - Integrated Silicon Solution, Inc

IS43DR16640C Scheda tecnica(HTML) 21 Page - Integrated Silicon Solution, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Scheda tecnica Scarica

Link URL