CLC418 datasheet(6/12 Pages) NSC

6 / 12 page

http://www.national.com

Figure 2: Inverting Gain

Select Rg to set the DC gain:

. At large gains,

Rg becomes small and will load the previous stage. This

can be solved by driving Rg with a low impedance buffer

like the CLC111, or increasing Rf and Rg. See the

AC Design (small signal bandwidth) sub-section for

the tradeoffs.

DC gain accuracy is usually limited by the tolerance of Rf

and Rg.

DC Gain (transimpedance)

Figure 3 shows a transimpedance circuit where the

current Iin is injected at the inverting node. The current

source’s output resistance is much greater than Rf.

The DC transimpedance gain is:

The recommended Rf is 3kΩ. Parasitic capacitance at

the inverting node may require a slight increase of Rf to

maintain a flat frequency response.

DC gain accuracy is usually limited by the tolerance of Rf.

Figure 3: Transimpedance Gain

DC Design (level shifting)

Figure 4 shows a DC level shifting circuit for inverting

gain configurations. Vref produces a DC output level shift

which is independent of the DC output

produced by Vin.

Figure 4: Level Shifting Circuit

DC Design (DC offsets)

The DC offset model shown in Fig. 5 is used to calculate

the output offset voltage. The equation for output offset

voltage is:

The current offset terms, IBN and IBI, do not track

each other. The specifications are stated in terms of

magnitude only. Therefore, the terms Vos, IBN, and IBI

can have either polarity.

Matching the equivalent

resistance seen at both input pins does not reduce the

output offset voltage.

Figure 5: DC Offset Model

DC Design (output loading)

RL, Rf, and Rg load the op amp output. The equivalent

load seen by the output in Figure 5 is:

RL(eq) =

RL || (Rf + Req2), non-inverting gain

RL || Rf, inverting and transimpedance gain

The equivalent output load (RL(eq)) needs to be large

enough so that the output current can produce the

required output voltage swing.

AC Design (small signal bandwidth)

The CLC418 current-feedback amplifier bandwidth is a

function of the feedback resistor (Rf), not of the DC voltage

gain (AV). The bandwidth is approximately proportional

As a rule, if Rf doubles, the bandwidth is cut in half.

Other AC

specifications

will

also

degraded.

Decreasing Rf from the recommended value increases

peaking, and

for very small values of Rf oscillation

will occur.

AC Design (minimum slew rate)

Slew rate influences the bandwidth of large signal

sinusoids. To determine an approximate value of slew

rate necessary to support a large sinusoid, use the

= −

1/2

CLC418

418 Fig3

0.1

µF

6.8

µF

VCC

0.1

µF

6.8

µF

VEE

3(5)

2(6)

1(7)

Iin

Vin

1/2

CLC418

418 Fig4

Vref

Rref

−

⋅

ref

eq1

eq2

= −

⋅

(

)⋅ +











 +

⋅

(

)

Req1

Req2

1/2

CLC418

418 Fig5

IBI

IBN

Vos

1/2

CLC418

418 Fig2

0.1

µF

6.8

µF

Vin

VCC

0.1

µF

6.8

µF

VEE

3(5)

2(6)

1(7)

{

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