CLC418 datasheet(8/12 Pages) NSC

8 / 12 page

http://www.national.com

Thermal Design

To calculate the power dissipation for the CLC418, follow

these steps for each individual amplifier:

1) Calculate the no-load op amp power:

Pamp = ICC • (VCC – VEE)

2) Calculate the output stage’s RMS power:

Po = (VCC – Vload) • Iload , where Vload and Iload

are the RMS voltage and current across the

external load

3) Calculate the total op amp RMS power:

Pt = Pamp + Po

Now calculate the total power dissipated in the package:

4) Sum Pt for both op amps to obtain Ptot

To calculate the maximum allowable ambient tempera-

ture, solve the following equation: Tamb = 175 – Ptot • θJA,

where

JA is the thermal resistance from junction

to ambient in °C/W, and Tamb is in °C. The Package

Thermal Resistance section contains the thermal

resistance for various packages.

Dynamic Range (input /output protection)

ESD diodes are present on all connected pins for protec-

tion from static voltage damage. For a signal that may

exceed the supply voltages, we recommend using diode

clamps at the amplifier’s input to limit the signals to less

than the supply voltages.

The CLC418’s output current can exceed the maximum

safe output current. To limit the output current to < 96mA:

Limit the output voltage swing with diode

clamps at the input

Make sure that

Vo(max) is the output voltage swing limit, and Io(max) is the

maximum safe output current.

Dynamic Range (input /output levels)

The

Electrical Characteristics section specifies the

Common-Mode Input Range and Output Voltage

Range; these voltage ranges scale with the supplies.

Output Current is also specified in the

Electrical

Characteristics section.

Unity gain applications are limited by the Common-Mode

Input Range. At greater non-inverting gains, the Output

Voltage Range becomes the limiting factor.

Inverting

gain applications are limited by the Output Voltage

Range (and by the previous amplifier’s ability to drive

Rg). For transimpedance gain applications, the sum of

the input currents injected at the inverting input pin of

the op amp needs to be:

, where Vmax is the

Output Voltage Range (see the

DC Gain (transimpedance)

sub-section for details).

The equivalent output load needs to be large enough

so that the minimum output current can produce the

required output voltage swing.

See the

DC Design

(output loading) sub-section for details.

Dynamic Range (noise)

The output noise defines the lower end of the CLC418’s

useful dynamic range. Reduce the value of resistors in

the circuit to reduce noise.

See the App Note

Noise Design of CFB Op Amp

Circuits for more details. Our SPICE models support noise

simulations.

Dynamic Range (distortion)

The distortion plots in the

Typical Performance

Characteristics section show distortion as a function

of load resistance, frequency, and output amplitude.

Distortion places an upper limit on the CLC418’s

dynamic range.

The CLC418’s output stage combines a voltage buffer

with a complementary common emitter current source.

The interaction between the buffer and the current

source produces a small amount of crossover distortion.

This distortion mechanism dominates at low output swing

and low resistance loads. To avoid this type of distortion,

use the CLC418 at high output swing.

Realized output distortion is highly dependent upon the

external circuit.

Some of the common external circuit

choices that can improve distortion are:

Short and equal return paths from the load to

the supplies

De-coupling capacitors of the correct value

Higher load resistance

Printed Circuit Board Layout

High frequency op amp performance is strongly dependent

on proper layout, proper resistive termination and

adequate power supply decoupling. The most important

layout points to follow are:

Use a ground plane

Bypass power supply pins with:

monolithic capacitors of about 0.1

µF place

less than 0.1” (3mm) from the pin

tantalum capacitors of about 6.8

µF for

large signal current swings or improved

power supply noise rejection;

we recommend a minimum of 2.2

µF

for any circuit

Minimize trace and lead lengths for components

between the inverting and output pins

Remove ground plane 0.1” (3mm) from all

input/output pads

For prototyping, use flush-mount printed circuit

board pins;

never use high profile DIP sockets.

Evaluation Board

Separate evaluation boards are available for proto-typing

and measurements. Additional information is available in

the evaluation board literature.

o(max)

≥

max

≤

CLC418 Scheda tecnica(PDF) 8 Page - National Semiconductor (TI)

CLC418 Scheda tecnica(HTML) 8 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Scheda tecnica Scarica

Link URL