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COP840C Scheda tecnica(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte COP840C
Spiegazioni elettronici  8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory, Comparator and Brown Out Detector
PDF  35 Pages
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP840C Scheda tecnica(HTML) 5 Page - National Semiconductor (TI)

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DC Electrical Characteristics (Continued)
−0˚C
≤ T
A ≤ + 70˚C for COP94x and −40˚C ≤ TA ≤ +85˚C for all others
Parameter
Conditions
Min
Typ
Max
Units
Output Current Levels
D Outputs:
Source
V
CC = 4.5V, VOH = 3.8V
−0.4
mA
V
CC = 2.5V, VOH = 1.8V
−0.2
mA
Sink
V
CC = 4.5V, VOL = 1.0V
10
mA
V
CC = 2.5V, VOH = 0.4V
2
mA
L4–L7 Output Sink
V
CC = 4.5V, VOL = 2.5V
15
mA
All Others
Source (Weak Pull-up Mode)
V
CC = 4.5V, VOH = 3.2V
−10
−110
µA
V
CC = 2.5V, VOH = 1.8V
−2.5
−33
µA
Source (Push-pull Mode)
V
CC = 4.5V, VOH = 3.8V
−0.4
mA
V
CC = 2.5V, VOH = 1.8V
−0.2
mA
Sink (Push-pull Mode)
V
CC = 4.5V, VOL = 0.4V
1.6
mA
V
CC = 2.5V, VOL = 0.4V
0.7
mA
TRI-STATE Leakage
−2.0
+2.0
µA
Allowable Sink/Source
Current Per Pin
D Outputs
15
mA
L4–L7 (Sink)
20
mA
All Others
3mA
Maximum Input Current
Room Temperature
±100
mA
without Latchup (Note 5)
RAM Retention Voltage, V
r
500 ns Rise and
2.0
V
Fall Time (Min)
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
Note 2: Rate of voltage change must be less than 10 V/mS.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set
high. The D port set to zero. All inputs tied to VCC. The comparator and the Brown Out circuits are disabled.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current
to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
www.national.com
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