COP840C datasheet(10/35 Pages) NSC

10 / 35 page

Pin Description

CC and GND are the power supply pins.

CKI is the clock input. This can come from an external

source, a R/C generated oscillator or a crystal (in conjunc-

tion with CKO). See Oscillator description.

RESET is the master reset input. See Reset description.

PORT I is a 4-bit Hi-Z input port.

PORT L is an 8-bit I/O port.

There are two registers associated with the L port: a data

bit can be individually configured under software control as

shown below:

Port L

Config.

Data

Setup

Hi-Z Input (TRI-STATE)

Input with Weak Pull-up

Push-pull Zero Output

Push-pull One Output

Three data memory address locations are allocated for this

port, one each for data register [00D0], configuration register

[00D1] and the input pins [00D2].

Port L has the following alternate features:

MIWU or MODOUT (high sink current capability)

MIWU (high sink current capability)

MIWU

MIWU or CMPIN+

MIWU or CMPIN−

MIWU or CMPOUT

The selection of alternate Port L functions is done through

registers WKEN [00C9] to enable MIWU and CNTRL2

[00CC] to enable comparator and modulator.

All eight L-pins have Schmitt Triggers on their inputs.

PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input

pins (G6, G7).

All eight G-pins have Schmitt Triggers on the inputs.

There are two registers associated with the G port: a data

bit can be individually configured under software control as

shown below:

Port G

Config.

Data

Setup

Hi-Z Input (TRI-STATE)

Input with Weak Pull-up

Push-pull Zero Output

Push-pull One Output

Three data memory address locations are allocated for this

port, one for data register [00D4], one for configuration reg-

ister [00D5] and one for the input pins [00D6]. Since G6 and

G7 are Hi-Z input only pins, any attempt by the user to con-

figure them as outputs by writing a one to the configuration

ration bits will return zeros. Note that the device will be

placed in the Halt mode by writing a “1” to the G7 data bit.

Six pins of Port G have alternate features:

CKO crystal oscillator output (selected by mask option)

or HALT restart input/general purpose input (if clock

option is R/C or external clock)

SI (MICROWIRE serial data input)

SK (MICROWIRE clock I/O)

SO (MICROWIRE serial data output)

TIO (timer/counter input/output)

INTR (an external interrupt)

Pins G2 and G1 currently do not have any alternate func-

tions.

The selection of alternate Port G functions are done through

registers PSW [00EF] to enable external interrupt and CN-

TRL1 [00EE] to select TIO and MICROWIRE operations.

PORT D is a four bit output port that is preset when RESET

goes low. One data memory address location is allocated for

the data register [00DC].

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

above 0.8 VCC to prevent the chip from entering special modes. Also

keep the external loading on D2 to less than 1000 pF.

Functional Description

The internal architecture is shown in the block diagram. Data

paths are illustrated in simplified form to depict how the vari-

ous logic elements communicate with each other in imple-

menting the instruction set of the device.

ALU and CPU Registers

The ALU can do an 8-bit addition, subtraction, logical or shift

operations in one cycle time. There are five CPU registers:

is the 8-bit Accumulator register

PC is the 15-bit Program Counter register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

is the 8-bit address register and can be auto incre-

mented or decremented.

is the 8-bit alternate address register and can be auto

incremented or decremented.

SP is the 8-bit stack pointer which points to the subroutine

stack (in RAM).

B, X and SP registers are mapped into the on chip RAM. The

B and X registers are used to address the on chip RAM. The

SP register is used to address the stack in RAM during sub-

routine calls and returns. The SP must be preset by software

upon initialization.

Memory

The memory is separated into two memory spaces: program

and data.

PROGRAM MEMORY

Program memory consists of 1024 x 8 ROM or 2048 x 8

ROM. These bytes of ROM may be instructions or constant

data. The memory is addressed by the 15-bit program

counter (PC). ROM can be indirectly read by the LAID in-

struction for table lookup.

DATA MEMORY

The data memory address space includes on chip RAM, I/O

and registers. Data memory is addressed directly by the in-

struction or indirectly through B, X and SP registers. The de-

vice has 64 or 128 bytes of RAM. Sixteen bytes of RAM are

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