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COP840C Scheda tecnica(PDF) 14 Page - National Semiconductor (TI) |
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COP840C Scheda tecnica(HTML) 14 Page - National Semiconductor (TI) |
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14 / 35 page ![]() Reset (Continued) input (SI), serial data output (SO) and serial shift clock (SK). Figure 6 shows the block diagram of the MICROWIRE/PLUS interface. The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/PLUS in- terface with the internal clock source is called the Master mode of operation. Operating the MICROWIRE/PLUS inter- face with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS , the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 4 details the different clock rates that may be selected. TABLE 4. SL1 SL0 SK Cycle Time 00 2t c 01 4t c 1x 8t c where, tc is the instruction cycle time. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 7 shows how two de- vice microcontrollers and several peripherals may be inter- connected using the MICROWIRE/PLUS arrangement. MASTER MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally by the device. The MICROWIRE/PLUS Master always initiates all data ex- changes ( Figure 7). The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration regis- ter. Table 5 summarizes the bit settings required for Master mode of operation. SLAVE MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port. The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register. Table 5 summarizes the settings required to enter the Slave mode of operation. DS011208-8 FIGURE 6. MICROWIRE/PLUS Block Diagram DS011208-23 FIGURE 7. MICROWIRE/PLUS Application www.national.com 14 |
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