COP8FGR7 datasheet(31/59 Pages) NSC

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9.0 Comparators

The device contains two differential comparators, each with

a pair of inputs (positive and negative) and an output. Ports

F1–F3 and F4–F6 are used for the comparators. The follow-

ing is the Port F assignment:

Comparator2 output

Comparator2 positive input

Comparator2 negative input

Comparator1 output

Comparator1 positive input

Comparator1 negative input

A Comparator Select Register (CMPSL) is used to enable

the comparators, read the outputs of the comparators inter-

nally, and enable the outputs of the comparators to the pins.

Two control bits (enable and output enable) and one result

bit are associated with each comparator. The comparator re-

sult bits (CMP1RD and CMP2RD) are read only bits which

will read as zero if the associated comparator is not enabled.

The Comparator Select Register is cleared with reset, result-

ing in the comparators being disabled. The comparators

should also be disabled before entering either the HALT or

IDLE modes in order to save power. The configuration of the

CMPSL register is as follows:

CMPSL REGISTER (ADDRESS X’00B7)

Reserved

CMP20E

CMP2RD

CMP2EN

CMP10E

CMP1RD

CMP1EN

Reserved

Bit 7

Bit 0

The CMPSL register contains the following bits:

Reserved These bits are reserved and must be zero

CMP20E

Selects pin I6 as comparator 2 output provided

that CMP2EN is set to enable the comparator

CMP2RD Comparator 2 result (this is a read only bit, which

will read as 0 if the comparator is not enabled)

CMP2EN

Enable comparator 2

CMP10E

Selects pin I3 as comparator 1 output provided

that CMPIEN is set to enable the comparator

CMP1RD Comparator 1 result (this is a read only bit, which

will read as 0 if the comparator is not enabled)

CMP1EN

Enable comparator 1

Note that the two unused bits of CMPSL may be used as

software flags.

Note: For compatibility with existing code and with existing Mask ROMMed

devices the bits of the CMPSL register will take precedence over the

associated Port F configuration and data output bits.

10.0 Interrupts

10.1 INTRODUCTION

Each device supports thirteen vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Each of the 13 maskable inputs has a fixed arbitration rank-

ing and vector.

Figure 26 shows the Interrupt Block Diagram.

DS101116-28

FIGURE 26. Interrupt Block Diagram

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