COP8FGR7 datasheet(43/59 Pages) NSC

43 / 59 page

13.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

Address

Contents

S/ADD REG

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads As

All Ones)

xx80 to xx93

Unused RAM Address Space (Reads

Undefined Data)

xx94

Port F data register, PORTFD

xx95

Port F configuration register, PORTFC

xx96

Port F input pins (read only), PORTFP

xx97 to xxAF

Unused address space (Reads

Undefined Data)

xxB0

Timer T3 Lower Byte

xxB1

Timer T3 Upper Byte

xxB2

Timer T3 Autoload Register T3RA Lower

Byte

xxB3

Timer T3 Autoload Register T3RA Upper

Byte

xxB4

Timer T3 Autoload Register T3RB Lower

Byte

xxB5

Timer T3 Autoload Register T3RB Upper

Byte

xxB6

Timer T3 Control Register

xxB7

Comparator Select Register

(Reg:CMPSL)

xxB8

UART Transmit Buffer (Reg:TBUF)

xxB9

UART Receive Buffer (Reg:RBUF)

xxBA

UART Control and Status Register

(Reg:ENU)

xxBB

UART Receive Control and Status

xxBC

UART Interrupt and Clock Source

xxBD

UART Baud Register (Reg:BAUD)

xxBE

UART Prescale Select Register

(Reg:PSR)

xxBF

Reserved for UART

xxC0

Timer T2 Lower Byte

xxC1

Timer T2 Upper Byte

xxC2

Timer T2 Autoload Register T2RA Lower

Byte

xxC3

Timer T2 Autoload Register T2RA Upper

Byte

xxC4

Timer T2 Autoload Register T2RB Lower

Byte

xxC5

Timer T2 Autoload Register T2RB Upper

Byte

xxC6

Timer T2 Control Register

xxC7

WATCHDOG Service Register

(Reg:WDSVR)

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

Address

Contents

S/ADD REG

xxC9

MIWU Enable Register (Reg:WKEN)

xxCA

MIWU Pending Register (Reg:WKPND)

xxCB to xxCF

Reserved

xxD0

Port L Data Register

xxD1

Port L Configuration Register

xxD2

Port L Input Pins (Read Only)

xxD3

Reserved for Port L

xxD4

Port G Data Register

xxD5

Port G Configuration Register

xxD6

Port G Input Pins (Read Only)

xxD7

Port I Input Pins (Read Only) (Actually

reads Port F input pins)

xxD8

Port C Data Register

xxD9

Port C Configuration Register

xxDA

Port C Input Pins (Read Only)

xxDB

Reserved for Port C

xxDC

Port D

xxDD to xxDF

Reserved for Port D

xxE0 to xxE5

Reserved for EE Control Registers

xxE6

Timer T1 Autoload Register T1RB Lower

Byte

xxE7

Timer T1 Autoload Register T1RB Upper

Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift Register

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

xxEC

Timer T1 Autoload Register T1RA Lower

Byte

xxED

Timer T1 Autoload Register T1RA Upper

Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to FB

On-Chip RAM Mapped as Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

S Register

0100–017F

On-Chip 128 RAM Bytes

0200–027F

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8FGE)

0300–037F

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8FGE)

Note: Reading memory locations 0070H–007FH (Segment 0) will return all

ones. Reading unused memory locations 0080H–0093H (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 4, Segment 5, … etc.) will return undefined data.

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