COP8FGR7 datasheet(15/59 Pages) NSC

15 / 59 page

5.0 Functional Description (Continued)

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

COMPARATORS:

CMPSL; CLEARED

WATCHDOG (if enabled):

The device comes out of reset with both the WATCH-

DOG logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor circuits are in-

hibited during reset. The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k t

C clock cycles. The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset. A Clock Monitor error

will cause an active low error output on pin G1. This error

output will continue until 16 t

C–32 tC clock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1 output will go high.

5.7.1 External Reset

The RESET input when pulled low initializes the device. The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset. During Power-Up initial-

ization, the user must ensure that the RESET pin is held low

until the device is within the specified V

CC voltage. An R/C

circuit on the RESET pin with a delay 5 times (5x) greater

than the power supply rise time or 15 µs whichever is

greater, is recommended. Reset should also be wide enough

to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

A recommended reset circuit for this device is shown in

Fig-

ure 10.

5.7.2 On-Chip Power-On Reset

The on-chip reset circuit is selected by a bit in the ECON reg-

ister. When enabled, the device generates an internal reset

as V

CC rises to a voltage level above 2.0V. The on-chip reset

circuitry is able to detect both fast and slow rise times on V

CC rise time between 10 ns and 50 ms).To guarantee an

on-chip power-on-reset, V

CCmust start at a voltage less than

the start voltage specified in the DC characteristics. Also, if

CC be lowered to the start voltage before powering back up

to the operating range. If this is not possible, it is recom-

mended that external reset be used.

Under no circumstances should the RESET pin be allowed

to float. If the on-chip Power-On Reset feature is being used,

RESET pin should be connected directly to V

CC. The output

of the power-on reset detector will always preset the Idle

timer to 0FFF(4096 t

C). At this time, the internal reset will be

generated.

If the Power-On Reset feature is enabled, the internal reset

will not be turned off until the Idle timer underflows. The inter-

nal reset will perform the same functions as external reset.

The user is responsible for ensuring that V

CC is at the mini-

mum level for the operating frequency within the 4096 t

C. Af-

ter the underflow, the logic is designed such that no addi-

tional internal resets occur as long as V

CC remains above

2.0V.

The contents of data registers and RAM are unknown follow-

ing the on-chip reset.

DS101116-14

RC >5x power supply rise time or 15 µs, whichever is greater.

FIGURE 10. Reset Circuit Using External Reset

DS101116-15

FIGURE 11. Reset Timing (Power-On Reset Enabled)

with V

CC Tied to RESET

DS101116-16

FIGURE 12. Reset Circuit Using Power-On Reset

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