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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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COP8FGR744J3 Scheda tecnica(PDF) 34 Page - National Semiconductor (TI) |
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COP8FGR744J3 Scheda tecnica(HTML) 34 Page - National Semiconductor (TI) |
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34 / 59 page  10.0 Interrupts (Continued) 10.3.1 VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is generated and so forth. If the only active inter- rupt is software trap, than E0 is generated. This number re- places the lower byte of the PC. The upper byte of the PC re- mains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration rank- ing. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitra- tion ranking. Figure 27 illustrates the different steps performed by the VIS instruction. Figure 28 shows a flowchart for the VIS instruc- tion. The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. DS101116-29 FIGURE 27. VIS Operation www.national.com 34 |
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