COP8FGR744J3 datasheet(8/59 Pages) NSC

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DC Electrical Characteristics (Continued)

−40˚C

≤ T

A ≤ +85˚C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Maximum Input Current without Latchup

(Note 7)

Room Temp.

±200

RAM Retention Voltage, Vr

2.0

CC Rise Time from a VCC ≥ 2.0V

(Note 10)

µs

Input Capacitance

(Note 9)

Load Capacitance on D2

(Note 9)

1000

AC Electrical Characteristics

−40˚C

≤ T

A ≤ +85˚C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

Crystal/Resonator, External

4.5V

≤ V

CC ≤ 5.5V

0.67

µs

R/C Oscillator (Internal)

4.5V

≤ V

CC ≤ 5.5V

µs

Frequency Variation (Note 9)

4.5V

≤ V

CC ≤ 5.5V

±35

External CKI Clock Duty Cycle (Note 9)

fr = Max

Rise Time (Note 9)

fr = 10 MHz Ext Clock

Fall Time (Note 9)

fr = 10 MHz Ext Clock

Output Propagation Delay (Note 8)

L = 2.2k, CL = 100 pF

PD1,tPD0

SO, SK

4.5V

≤ V

CC ≤ 5.5V

0.7

µs

All Others

4.5V

≤ V

CC ≤ 5.5V

1.0

µs

MICROWIRE Setup Time (t

UWS) (Note

11)

MICROWIRE Hold Time (t

UWH) (Note

11)

MICROWIRE Output Propagation

Delay (t

UPD) (Note 11)

220

Input Pulse Width (Note 9)

Interrupt Input High Time

Interrupt Input Low Time

Timer 1, 2, 3, Input High Time

Timer 1 2, 3, Input Low Time

Reset Pulse Width

µs

Note 3: tC = Instruction cycle time.

Note 4: Maximum rate of voltage change must be < 0.5 V/ms.

Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to VCC and outputs driven low

but not connected to a load.

Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal

or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-

grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers

to HALT mode entered via setting bit 7 of the G Port data register.

Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when

biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two

pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes

ESD transients.

Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 9: Parameter characterized but not tested.

Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.

Note 11: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See and the MICROWIRE

operation description.

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