COP8FGR744J3 datasheet(14/59 Pages) NSC

14 / 59 page

5.0 Functional Description (Continued)

Memory address ranges 0200 to 027F and 0300 to 037F are

unavailable on the COP8FGx5 and, if read, will return under-

fined data.

5.5 ECON (CONFIGURATION) REGISTER

For compatibility with COP8FGx7 devices, mask options are

defined by an ECON Configuration Register which is pro-

grammed at the same time as the program code. Therefore,

the register is programmed at the same time as the program

memory.

The format of the ECON register is as follows:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR

SECURITY

CKI 2

CKI 1

WATCH

F-Port

HALT

DOG

Bit 7

= x

This is for factory test. The polarity is “Don’t

Care.”

Bit 6

= 1

Power-on reset enabled.

= 0

Power-on reset disabled.

Bit 5

= 1

Security enabled.

Bits 4,3=0,0 External CKI option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI is clock input.

= 0, 1 R/C oscillator option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI clock input. Internal R/C

components are supplied for maximum R/C

frequency.

= 1, 0 Crystal oscillator with on-chip crystal bias

resistor disabled. G7 (CKO) is the clock

generator output to crystal/resonator.

= 1, 1 Crystal oscillator with on-chip crystal bias

resistor enabled. G7 (CKO) is the clock

generator output to crystal/resonator.

Bit 2

= 1

WATCHDOG feature disabled. G1 is a gen-

eral purpose I/O.

= 0

WATCHDOG feature enabled. G1 pin is

WATCHDOG output with weak pullup.

Bit 1

= 1

Force port I compatibility. Disable port F

outputs and pull-ups. This is intended for

compatibility with existing code and Mask

ROMMed devices only. This bit should be

programmed to 0 for all other applications.

= 0

Enable full port F capability.

Bit 0

= 1

HALT mode disabled.

= 0

HALT mode enabled.

5.6 USER STORAGE SPACE IN EPROM

The ECON register is outside of the normal address range of

the ROM and can not be accessed by the executing soft-

ware.

The COP8 assembler defines a special ROM section type,

CONF, into which the ECON may be coded. Both ECON and

User Data are programmed automatically by programmers

that are certified by National.

The following examples illustrate the declaration of ECON

and the User information.

Syntax:

[label:] .sect

econ, conf

.db

value

;1 byte,

;configures options

.db

.endsect

; up to 8 bytes

Example: The following sets a value in the ECON register

and User Identification for a COP8FGR728M7. The ECON

bit values shown select options: Power-on enabled, Security

disabled, Crystal oscillator with on-chip bias disabled,

WATCHDOG enabled and HALT mode enabled.

.sect

econ, conf

.db

0x55

;por, xtal, wd, halt

.db

'my v1.00' ;user data declaration

.endsect

5.7 RESET

The devices are initialized when the RESET pin is pulled low

or the On-chip Power-On Reset is enabled.

The following occurs upon initialization:

Port L: TRI-STATE (High Impedance Input)

Port C: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input)

Port F: TRI-STATE (High Impedance Input)

Port D: HIGH

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

T3CNTRL: CLEARED

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET with crystal clock option

(power already applied)

UNAFFECTED after RESET with R/C clock option

(power already applied)

RANDOM after RESET at power-on

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

DS101116-13

FIGURE 9. Reset Logic

COP8FGR744J3 Scheda tecnica(PDF) 14 Page - National Semiconductor (TI)

COP8FGR744J3 Scheda tecnica(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Scheda tecnica Scarica

Link URL