Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

DP83256VF Scheda tecnica(PDF) 100 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte DP83256VF
Spiegazioni elettronici  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256VF Scheda tecnica(HTML) 100 Page - National Semiconductor (TI)

Back Button DP83256VF Datasheet HTML 96Page - National Semiconductor (TI) DP83256VF Datasheet HTML 97Page - National Semiconductor (TI) DP83256VF Datasheet HTML 98Page - National Semiconductor (TI) DP83256VF Datasheet HTML 99Page - National Semiconductor (TI) DP83256VF Datasheet HTML 100Page - National Semiconductor (TI) DP83256VF Datasheet HTML 101Page - National Semiconductor (TI) DP83256VF Datasheet HTML 102Page - National Semiconductor (TI) DP83256VF Datasheet HTML 103Page - National Semiconductor (TI) DP83256VF Datasheet HTML 104Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 100 / 144 page
background image
60 Signal Descriptions (Continued)
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consist of a reset signal and user definable enable signals
Symbol
Pin
IO
Description
E
RST
71
I
Reset
An active low TTL input signal which clears all registers The signal must be kept asserted for a
minimum amount of time Once the ERST signal is asserted the PLAYERa device should be allowed
the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to
zero (ie Stop Mode) See section 42 Stop Mode of Operation for more information
EP0
41
O
User Definable Enable Pin 0
A TTL output signal allowing control of external logic through the Control
Bus Interface EP0 is asserteddeasserted through Enable Bit 0 (EB0) of the User Definable Register
(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is
asserted
EP1
43
O
User Definable Enable Pin 1
A TTL output signal allowing control of external logic through the Control
Bus Interface EP1 is asserteddeasserted through Enable Bit 1 (EB1) of the User Definable Register
(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is
asserted
100



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com