AD9985SLASHPCB datasheet(19/32 Pages) AD

19 / 32 page

AD9985

Rev. 0 | Page 19 of 32

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP

IDENTIFICATION

7–0

Chip Revision

An 8-bit register that represents the silicon revision.

PLL DIVIDER CONTROL

7–0

PLL Divide Ratio MSBs

The 8 most significant bits of the 12-bit PLL divide

ratio PLLDIV. The operational divide ratio is

PLLDIV + 1.

The PLL derives a master clock from an incoming

Hsync signal. The master clock frequency is then

divided by an integer value, such that the output is

phase-locked to Hsync. This PLLDIV value

determines the number of pixel times (pixels plus

horizontal blanking overhead) per line. This is

typically 20% to 30% more than the number of active

pixels in the display.

The 12-bit value of the PLL divider supports divide

ratios from 2 to 4095. The higher the value loaded in

this register, the higher the resulting clock frequency

with respect to a fixed Hsync frequency.

VESA has established some standard timing

specifications that assist in determining the value for

PLLDIV as a function of horizontal and vertical

display resolution and frame rate (Table 9).

However, many computer systems do not conform

precisely to the recommendations, and these numbers

should be used only as a guide. The display system

manufacturer should provide automatic or manual

means for optimizing PLLDIV. An incorrectly set

PLLDIV will usually produce one or more vertical

noise bars on the display. The greater the error, the

greater the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH).

The AD9985 updates the full divide ratio only when

the LSBs are changed. Writing to the MSB by itself will

not trigger an update.

7–4

PLL Divide Ratio LSBs

The 4 least significant bits of the 12-bit PLL divide

ratio PLLDIV. The operational divide ratio is

PLLDIV + 1.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH). The AD9985

updates the full divide ratio only when this register is

written to.

CLOCK GENERATOR CONTROL

7–6

VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the

desired operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high

frequencies. For this reason, to output low pixel rates

and still get good jitter performance, the PLL actually

operates at a higher frequency but then divides down

the clock rate afterwards.

Table 11 shows the pixel rates for each VCO range setting. The

PLL output divisor is automatically selected with the

VCO range setting.

Table 11. VCO Ranges

Pixel Clock Range (MHz)

PV1

PV0

AD9985KSTZ

AD9985BSTZ

12–32

12–30

32–64

30–60

64–110

60–110

110–140

The power-up default value is 01.

5–3

CURRENT Charge Pump Current

Three bits that establish the current driving the loop

filter in the clock generator.

Table 12. Charge Pump Currents

CURRENT

Current (µA)

000

001

100

010

150

011

250

100

350

101

500

110

750

111

1500

CURRENT must be set to correspond with the desired

operating frequency (incoming pixel rate).

The power-up default value is current = 001.

7–3

Clock Phase Adjust

A 5-bit value that adjusts the sampling phase in 32

steps across one pixel time. Each step represents an

11.25° shift in sampling phase.

The power-up default value is 16.

AD9985/PCB Scheda tecnica(PDF) 19 Page - Analog Devices

AD9985/PCB Scheda tecnica(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Scheda tecnica Scarica

Link URL