AD9985SLASHPCB datasheet(23/32 Pages) AD

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AD9985

Rev. 0 | Page 23 of 32

Red Clamp Select

This bit determines whether the Red channel is

clamped to ground or to midscale. For RGB video, all

three channels are referenced to ground. For YCbCr

(or YUV), the Y channel is referenced to ground, but

the CbCr channels are referenced to midscale.

Clamping to midscale actually clamps to Pin 37.

Table 28. Red Clamp Select Settings

Clamp

Function

Clamp to Ground

Clamp to Midscale (Pin 37)

The default setting for this register is 0.

Green Clamp Select

This bit determines whether the Green channel is

clamped to ground or to midscale.

Table 29. Green Clamp Select Settings

Clamp

Function

Clamp to Ground

Clamp to Midscale (Pin 37)

The default setting for this register is 0.

Blue Clamp Select

This bit determines whether the Blue channel is

clamped to ground or to midscale.

Table 30. Blue Clamp Select Settings

Clamp

Function

Clamp to Ground

Clamp to Midscale (Pin 37)

The default for this register is 0.

7–0

Sync Separator Threshold

This register is used to set the responsiveness of the

sync separator. It sets how many internal 5 MHz clock

periods the sync separator must count to before

toggling high or low. It works like a low-pass filter to

ignore Hsync pulses in order to extract the Vsync

signal. This register should be set to some number

greater than the maximum Hsync pulsewidth. Note

that the sync separator threshold uses an internal

dedicated clock with a frequency of approximately

5 MHz.

The default for this register is 32.

7–0

Pre-Coast

This register allows the coast signal to be applied prior

to the Vsync signal. This is necessary in cases where

pre-equalization pulses are present. The step size for

this control is one Hsync period.

The default is 0.

7–0

Post-Coast

This register allows the coast signal to be applied

following the Vsync signal. This is necessary in cases

where post-equalization pulses are present. The step

size for this control is one Hsync period.

The default is 0.

Hsync Detect

This bit is used to indicate when activity is detected on

the Hsync input pin (Pin 30). If Hsync is held high or

low, activity will not be detected.

Table 31. Hsync Detection Results

Detect

Function

No Activity Detected

Activity Detected

The Sync Processing Block Diagram (Figure 14) shows

where this function is implemented.

AHS – Active Hsync

This bit indicates which Hsync input source is being

used by the PLL (Hsync input or Sync-on-Green).

Bits 7 and 1 in this register determine which source is

used. If both Hsync and SOG are detected, the user

can determine which has priority via Bit 3 in

Bit 4 in Register 0EH. If the override bit is set to

Logic 1, this bit will be forced to whatever the state of

Bit 3 in Register 0EH is set to.

Table 32. Active Hsync Results

Bit 7

Bit 1

Bit 4,

(Hsync

(SOG

Reg 0EH

Detect)

(Override)

AHS

Bit 3 in 0EH

AHS = 0 means use the Hsync pin input for Hsync.

AHS = 1 means use the SOG pin input for Hsync.

The override bit is in Register 0EH, Bit 4.

Detected Hsync Input Polarity Status

This bit reports the status of the Hsync input polarity

detection circuit. It can be used to determine the

polarity of the Hsync input. The detection circuit’s

location is shown in the Sync Processing Block

Diagram (Figure 14).

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