AD9985SLASHPCB datasheet(21/32 Pages) AD

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AD9985

Rev. 0 | Page 21 of 32

MODE CONTROL 1

Hsync Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Hsync signal going

into the PLL.

Table 13. Hsync Input Polarity Override Settings

Override Bit

Function

Hsync Polarity Determined by Chip

Hsync Polarity Determined by User

The default for Hsync polarity override is 0 (polarity

determined by chip).

HSPOL Hsync Input Polarity

A bit that must be set to indicate the polarity of the

Hsync signal that is applied to the PLL Hsync input.

Table 14. Hsync Input Polarity Settings

HSPOL

Function

Active Low

Active High

Active Low means the leading edge of the Hsync pulse

is negative going. All timing is based on the leading

edge of Hsync, which is the falling edge. The rising

edge has no effect.

Active high is inverted from the traditional Hsync,

with a positive-going pulse. This means that timing

will be based on the leading edge of Hsync, which is

now the rising edge.

The device will operate if this bit is set incorrectly, but

the internally generated clamp position, as established

by Clamp Placement (Register 05H), will not be

placed as expected, which may generate clamping

errors.

The power-up default value is HSPOL = 1.

Hsync Output Polarity

This bit determines the polarity of the Hsync output

and the SOG output. Table 15 shows the effect of this

option. SYNC indicates the logic state of the sync

pulse.

Table 15. Hsync Output Polarity Settings

Setting

SYNC

Logic 1 (Positive Polarity)

Logic 0 (Negative Polarity)

The default setting for this register is 0.

Active Hsync Override

This bit is used to override the automatic Hsync

selection, To override, set this bit to Logic 1. When

overriding, the active Hsync is set via Bit 3 in this

Table 16. Active Hsync Override Settings

Override

Result

Autodetermines the Active Interface

Override, Bit 3 Determines the Active Interface

The default for this register is 0.

Active Hsync Select

This bit is used under two conditions. It is used to

select the active Hsync when the override bit is set

(Bit 4). Alternately, it is used to determine the active

Hsync when not overriding but both Hsyncs are

detected.

Table 17. Active HSYNC Select Settings

Select

Result

HSYNC Input

Sync-on-Green Input

The default for this register is 0.

Vsync Output Invert

This bit inverts the polarity of the Vsync output.

Table 18 shows the effect of this option.

Table 18. Vsync Output Invert Settings

Setting

Vsync Output

Invert

No Invert

The default setting for this register is 0.

Active Vsync Override

This bit is used to override the automatic Vsync

selection. To override, set this bit to Logic 1. When

overriding, the active interface is set via Bit 0 in this

Table 19. Active Vsync Override Settings

Override

Result

Autodetermines the Active Vsync

Override, Bit 0 Determines the Active Vsync

The default for this register is 0.

Active Vsync Select

This bit is used to select the active Vsync when the

override bit is set (Bit 1).

Table 20. Active Vsync Select Settings

Select

Result

Vsync Input

Sync Separator Output

The default for this register is 0.

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