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DP83916 Scheda tecnica(PDF) 73 Page - National Semiconductor (TI) |
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DP83916 Scheda tecnica(HTML) 73 Page - National Semiconductor (TI) |
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73 / 96 page ![]() 70 AC and DC Specifications (Continued) AC Specifications BUS CLOCK TIMING TLF11722 – 58 Number Parameter 20 MHz Units Min Max T1 Bus Clock Low Time 225 ns T2 Bus Clock High Time 225 ns T3 Bus Clock Cycle Time (Note 2) 50 100 ns POWER-ON RESET TLF11722 – 59 NON POWER-ON RESET TLF11722 – 60 Number Parameter 20 MHz Units Min Max T4 USRk10l Setup to RST 10 ns T5 USRk10l Hold from RST 20 ns T6 Power-On Reset High (Notes 1 2) 10 TXC T8 Reset Pulse Width (Notes 1 2) 10 TXC Note 1 The reset time is determined by the slower of BSCK or TXC If BSCK l TXC T6 and T8 equal 10 TXCs If BSCK k TXC T6 and T8 equal 10 BSCKs (T3) Note 2 These specifications are not tested 73 |
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