Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

DP83916 Scheda tecnica(PDF) 74 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte DP83916
Spiegazioni elettronici  SONICTM-16 Systems-Oriented Network Interface Controller
PDF  96 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83916 Scheda tecnica(HTML) 74 Page - National Semiconductor (TI)

Back Button DP83916 Datasheet HTML 70Page - National Semiconductor (TI) DP83916 Datasheet HTML 71Page - National Semiconductor (TI) DP83916 Datasheet HTML 72Page - National Semiconductor (TI) DP83916 Datasheet HTML 73Page - National Semiconductor (TI) DP83916 Datasheet HTML 74Page - National Semiconductor (TI) DP83916 Datasheet HTML 75Page - National Semiconductor (TI) DP83916 Datasheet HTML 76Page - National Semiconductor (TI) DP83916 Datasheet HTML 77Page - National Semiconductor (TI) DP83916 Datasheet HTML 78Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 74 / 96 page
background image
70 AC and DC Specifications (Continued)
MEMORY WRITE BMODE e 0 SYNCHRONOUS MODE (one wait-state shown)
TLF11722 – 61
Number
Parameter
20 MHz
Units
Min
Max
T9
BSCK to Address Valid
34
ns
T10
Address Hold Time from BSCK
5
ns
T11
BSCK to ADS ECS Low
34
ns
T12
BSCK to ADS ECS High
34
ns
T15
ADS High Width (Note 2)
bcyc-5
ns
T32
RDYi Setup to BSCK
30
ns
T33
RDYi Hold from BSCK
5
ns
T36
BSCK to Memory Write Data Valid
70
ns
T37
BSCK to MWR (Write) Valid (Note 1)
30
ns
T40
Write Data Hold Time from BSCK
10
ns
Note 1
For successive read operations MWR remains low and for successive write operations MWR remains high during a transfer During RDA and TDA
transfers the MWR signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge
of a Ti (idle) state that is inserted between the read and the write operation
Note 2
bcyc e bus clock cycle time (T3)
74



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com