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DP83916 Scheda tecnica(PDF) 91 Page - National Semiconductor (TI) |
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DP83916 Scheda tecnica(HTML) 91 Page - National Semiconductor (TI) |
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91 / 96 page ![]() 70 AC and DC Specifications (Continued) ENDEC RECEIVE TIMING (INTERNAL ENDEC MODE) TLF11722 – 78 ENDEC COLLISION TIMING TLF11722 – 79 Number Parameter Min Max Units T102 Receive Clock Duty Cycle Time (Note 1) 40 60 ns T105 Carrier Sense on Time 70 ns T106 Data Acquisition Time 700 ns T107 Receive Data Output Delay 150 ns T108 Receive Data Valid from RXC 10 ns T109 Receive Data Stable Valid Time 90 ns T112 Carrier Sense Off Delay (Note 2) 155 ns T113 Minimum Number of RXCs after CRS Low 5 rcyc (Note 3) T114 Collision Turn On Time 55 ns T115 Collision Turn Off Time 250 ns Note 1 This parameter is measured at the 50% point of each clock edge Note 2 When CRSi goes low it remains low for a minimum of 2 receive clocks (RXCs) Note 3 rcyc e receive clocks 91 |
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