PC87393F datasheet(45/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.10.10 SuperI/O Configuration 9 Register (SIOCF9)

Location:

Index 29h

Type:

Varies per bit

Bit

43210

Name

Reserved

Module

Enable

Status

Valid Multi-

plier Clock

Status

Clock

Enable

SuperI/O Chip Clock

Source

Reset

00010

Bit

Description

7-5

Reserved

Module Enable Status. This bit defines the status of all the PC8739x modules with exception of the X-Bus. This

bit is read only.

0: All modules disabled

1: At least one module enabled

Valid Multiplier Clock Status. This bit is read only.

0: On-chip clock frozen

1: On-chip clock stable and toggling

Clock Enable. This bit enables the 48 and 24 MHz clock to the SuperI/O modules. When the SuperI/O chip

clock source is set to 48 MHz, this bit enables the path from the input CLKIN pin. When the clock source is set

to 32.768 KHz or 14.31818 MHz, this bit enables the clock multiplier.This is a read/write bit that is reset by

hardware reset only.

0: Clock disabled (default)

1: Clock enabled

1-0

SuperI/O Chip Clock Source. These bits define the clock source for the SuperI/O chip that is fed via the CLKIN

pin. On power-up (only), these bits are read or write and assume their default value. Once they are written, they

become read only bits.

Bits

Function

1 0

0 0

Clock source is 48 MHz

0 1

Clock source is the on-chip clock multiplier fed by 32.768 KHz

1 0

Clock source is the on-chip clock multiplier fed by 14.31818 MHz (default)

1 1

Reserved

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