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PC87393F Scheda tecnica(PDF) 59 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte PC87393F
Spiegazioni elettronici  100-Pin LPC SuperI/O Devices for Portable Applications
PDF  148 Pages
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87393F Scheda tecnica(HTML) 59 Page - National Semiconductor (TI)

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2.0 Device Architecture and Configuration (Continued)
59
www.national.com
2.15.5
GPIO Pin Configuration Register
This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO
Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hard-
ware to 44h, except for ports 2 and 3, that are reset to 04h, and GPIO36 which resets to 00h.
Location:
Index F1h
Type:
R/W
Ports: 0 and 1 (with event detection capability)
Ports 2 and 3 (without event detection capability)
Bit
76543210
Name
Reserved
Event
Debounce
Enable
Event
Polarity
Event Type
Lock
Pull-Up
Control
Output
Type
Output
Enable
Reset
01000100
Bit
76543210
Name
Reserved
Lock
Pull-Up
Control
Output
Type
Output
Enable
Reset
00000100
Bit
Description
7
Reserved
6
Event Debounce Enable. (Ports 0 and 1 with event detection capability). Enables transferring the signal only
after a predetermined debouncing period of time.
0: Disabled
1: Enabled (default)
Reserved. (Ports 2 and 3). Always 0.
5
Event Polarity. (Ports 0 and 1 with event detection capability). This bit defines the polarity of the signal that
issues an interrupt from the corresponding GPIO pin (falling/low or rising/high).
0: Falling edge or low level input (default)
1: Rising edge or high level input
Reserved. (Ports 2 and 3). Always 0.
4
Event Type. (Ports 0 and 1 with event detection capability). This bit defines the type of the signal that issues an
interrupt from the corresponding GPIO pin (edge or level).
0: Edge input (default)
1: Level input
Reserved. (Ports 2 and 3). Always 0.
3
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O
Configuration 1 register, SIOCF1).
0: No effect (default)
1: Direction, output type, pull-up and output value locked



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