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PC87393F Scheda tecnica(PDF) 113 Page - National Semiconductor (TI) |
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PC87393F Scheda tecnica(HTML) 113 Page - National Semiconductor (TI) |
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113 / 148 page ![]() 7.0 X-Bus Extension (Continued) 113 www.national.com Bit Description 7-2 Reserved 1 Read/Write Extended Mode Enable. When set to 1, enables the separation of the I/O read and write transactions from pins XRD & XWR to pins XIORD & XIOWR, leaving the memory and FWH transactions to be routed to XRD and XWR. 0: Disabled (default) 1: Enabled 0 Latch Address Mode Enabled. When set to 1, enables three phases of addresses to be latched on the data pins. Reset value of this bit is set by the XCNF2-0 strap inputs. See Section 1.5.11 for the definition of this setting. 0: Disabled 1: Enabled |
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