TAS3108DCPR datasheet(39/63 Pages) TI1

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7.1.2

Master Mode LRCLK Divider

7.1.3

SCLKIN and SCLKOUT Clock Divide

7.1.4

MCLK, SCLK Ratio (Master Mode Only)

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

Bits 26–24 (Y2, Y1, and Y0) define the ratio between SCLK and LRCLK, but only have meaning in the

clock-master mode where LRCLK is an output. In the clock-slave mode, LRCLK is an input.

DESCRIPTION

LRCLK out = SCLK/32

LRCLK out = SCLK/64

LRCLK out = SCLK/128

LRCLK out = SCLK/192

LRCLK out = SCLK/256

LRCLK out = SCLK/384

LRCLK out = SCLK/512

LRCLK out = SCLK/32

Bits 21–19 (X2, X1, and X0) define the ratio between SCLKIN and SCLKOUT. These control bits are only

used when the input and output rates are different, which can happen if TDM and discrete modes are both

used (for example, input is TDM and output is discrete). Normally, these bits are set to 000, so that

SCLKOUT1 (input SCLK) and SLCKOUT2 (output SCLK) are the same. (Note that SCLKIN is not the

input SCLK, but is used in clock-slave mode to derive SCLKOUT1.)

DESCRIPTION

X MUX out = IMS_MUX (master/slave SCLK)

X MUX out = IMS_MUX/2

X MUX out = IMS_MUX/3

X MUX out = IMS_MUX/4

X MUX out = IMS_MUX/6

X MUX out = IMS_MUX/8

X MUX out = IMS_MUX/16

X MUX out = IMS_MUX/32

Bits 18–16 (Z2, Z1, and Z0) define the ratio between MCLK and SCLK when the TAS3108/TAS3108IA is

the clock master. In clock-slave mode, these bits are don't care.

DESCRIPTION

Z MUX out = MCLK (MCLKI or crystal oscillator)

Z MUX out = MCLK/2

Z MUX out = MCLK/3

Z MUX out = MCLK/4

Z MUX out = MCLK/6

Z MUX out = MCLK/8

Z MUX out = MCLK/16

Z MUX out = MCLK/32

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