TAS3108DCPR datasheet(12/63 Pages) TI1

Il numero della parte	TAS3108DCPR

Spiegazioni elettronici	AUDIO DIGITAL SIGNAL PROCESSORS

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Produttore elettronici	TI1 [Texas Instruments]

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3.8.2

2 Channel Left Justified Timing

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelLeft-JustifiedStereoInput

T0034-02

MSB

LSB

SCLK

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when

right channel data is transmitted. SCLK is a bit clock running at 64

× f

S which clocks in each bit of the

data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written

MSB first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing

data-bit positions.

Figure 3-3. Left justified 64-fS Format

Physical Characteristics

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