CY7C68310
Document 38-08030 Rev. *H
Page 5 of 34
4.3
Detailed Pin Descriptions
4.3.1
DP, DM
DP and DM are the high-speed USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. See section 15.0 for PCB layout guidelines.
4.3.2
RSDP, RSDM
RSDP and RSDM are the full-speed USB signaling pins, and
they should be tied to the DP and DM pins through 39
Ω
resistors. RSDP and RSDM also function as current sinks for
termination during high-speed operation.
4.3.3
TEST[0:3]
The test pins control the various test modes of the
CY7C68310. Most test modes are reserved for ASIC fabri-
cation, but the following table outlines the test modes available
for device manufacturing environments. The test pins must be
tied to GND for normal operation.
4.3.4
XI, XO
The CY7C68310 requires a 30-MHz signal to derive internal
timing. Typically a 30-MHz (2.5V tolerant, parallel-resonant
fundamental mode) crystal is used, but a 30-MHz (2.5V, 50%
duty cycle) square wave from another source can also be
used. If a crystal is used, connect the pins to XI and XO, and
also through 20pF capacitors to GND as shown in Figure 8-1.
If an alternate clock source is used, apply it to XI and leave XO
open.
4.3.5
nEJECT
The nEJECT input pin provides a means to communicate an
Eject button push to the ATA/ATAPI device via event notifi-
cation as well as a way to cause a USB Remote-wakeup.
During normal operation, asserting nEJECT for 10ms
indicates that a media eject has been requested. If the
CY7C68310 is in a suspend state, and if remote wakeup is
enabled by the USB host, a state change on this pin will
immediately cause the CY7C68310 to perform a USB remote
wakeup event.
4.3.6
SYSIRQ
The SYSIRQ pin provides a way for systems to request service
from host software by use of the USB Interrupt pipe. If the
CY7C68310 has no pending interrupt data to return, USB
interrupt pipe data requests are NAKed. If pending data is
available, CY7C68310 returns 16 bits of data indicating the
state of the DISKRDY pin, the HS_MODE signal (that
indicates whether CY7C68310 is operating in high-speed or
full-speed), the VBUSPWRD pin, the User-Defined values
from bits [7:3] of address 0xE of the configuration space, and
the GPIO Pins. Table 4-2 shows the bitmap for the data
returned on the interrupt pipe, and the figure beneath it depicts
the latching algorithm incorporated by CY7C68310.
Table 4-1. CY7C68310 Test Modes
Test Mode
Description
0000
Normal Mode. This is the default mode of operation.
0001
Reserved.
0010
Limbo Mode. All output pins set to high-Z during Limbo mode operation with the exception of the XO pin. The XO
pin output cell does not have high-Z control (always enabled), and must be disabled or disconnected by other
means. To enter Limbo Mode, nRESET must be toggled after the Test pins are set to ‘0010’.
0011
Input xnorTree Mode. This mode tests the connectivity of all dedicated inputs and outputs. While in the Input
xnorTree Mode of operation, all bi-directional pins are wired as chain outputs. The results of the connectivity
procedure will be seen on all bidirectional pins. Chain Inputs (in order): VBUSPWRVLD, VBUSPWRD, DISKRDY,
ATAIRQ, IORDY, DMARQ, nRESET, ATAEN, DRVPWRVLD, SYSIRQ, nEJECT Chain Outputs (in order):
GPIO[2:0], DD[15:0], SDA_nIMODE.
0100
Bi-di xnorTree Mode. This mode test the connectivity of all bi-directional inputs. While in the Bi-di xnor Tree Mode
of operation, all bi-directional pins are wired as inputs and become part of the xnor Tree chain. The results of the
connectivity procedure will be seen on all output only pins. Chain Inputs: GPIO[0], GPIO[1], GPIO[2], DD[7], DD[8],
DD[6], DD[0], DD[5], DD[10], DD[4], DD[11], DD[3], DD[12], DD[2], DD[13], DD[1], DD[14], DD[0], DD[15],
SDA_nIMODE. Chain Outputs: nPWR500, nATARST, nDIOW, nDIOR, nDMACK, ATAPUEN, nCS[1:0], DA[2:0],
LOWPWR, SCL
0101–1111
Reserved.
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