CY7C68310
Document 38-08030 Rev. *H
Page 3 of 34
4.2
Pin Overview
Pin
Number
Pin Name
Pin
Direction
Pin Type
Pin Description
2
RPU
O
USB Output
D+ pull-up source. Power source for 1.5k pull-up resistor attached
to D+ during full-speed operation.
5
RSDP
O
USB I/O
USB full-speed output buffer (D+). RSDP also functions as a
current sink for termination during high-speed operation.
6
DP
I/O
USB I/O
USB high-speed I/O buffer (D+).
8
DM
I/O
USB I/O
USB high-speed I/O buffer (D-).
9
RSDM
O
USB I/O
USB full-speed output buffer (D-). RSDM also functions as a
current sink for termination during high-speed operation.
18–20, 25
TEST[0:3]
I
5V-tolerant input
buffer
Active HIGH. ASIC fabrication and manufacturing test mode select.
These pins must be tied to GND during normal operation.
22
XI
I
OSC input
(2.5V-tolerant)
30-MHz crystal input.
23
XO
O
OSC output
30-MHz crystal output.
26
nEJECT
I
5V-tolerant
Schmitt input
Active LOW. Media eject or remote wakeup requested. Tie to +3.3V
if functionality is not used.
27
SYSIRQ
I
5V-tolerant
Schmitt input
Active HIGH. USB interrupt request. Tie to GND if functionality is not
used.
28
DRVPWRVLD
I
5V-tolerant
Schmitt input
Configurable polarity. Device Presence Detect. This pin must not
be allowed to float if functionality is not utilized.
29
ATAEN
I
5V-tolerant
Schmitt input
Active HIGH. ATA interface enable.
‘1’ = normal ATA operation
‘0’ = High-Z ATA interface pins and ATA interface logic halted
30–32
GPIO[0:1],
GPIO2_nHS
I/O
3.3V drive,
5V-tolerant,
6-mA IOL,
Schmitt input
General purpose I/O pins. The GPIO pins must be tied to GND if
functionality is not utilized. If the hs_indicator config bit is set, the
GPIO2_nHS pin will reflect the operating speed of the device.
‘1’ = full-speed operation
‘0’ = high-speed operation
33
SCANEN
I
5V tolerant
input buffer
Active HIGH. ASIC test pin. This pin must be tied to GND during
normal operation.
34
LOWPWR
O
high-Z driver,
5V-tolerant,
6-mA IOL
Active HIGH. USB suspend indicator.
‘0’ = Chip active. VBUS power up to 100 mA granted.
‘High-Z’ = Chip suspend. VBUS system current limited to USB
suspend mode value.
35
nRESET
I
5V-tolerant
Schmitt input
Active LOW. Asynchronous chip reset.
36
nATARST
O
3.3V drive,
5V-tolerant,
6-mA IOL
Active LOW. ATA reset signal.
37, 38
TMC[1:2]
I
3.3V input
Active HIGH. ASIC test pins. These pins must be tied to GND during
normal operation.
56, 54, 52,
49,46, 44,
42, 39, 41,
43, 45, 48,
51, 53, 55,
57
DD[0:15]
I/O
3.3V drive,
5V-tolerant,
6-mA IOL,
Schmitt input
ATA data signals.
58
DMARQ
I
5V tolerant
Schmitt input
ATA control signal.
62
nDIOW
O
3.3V drive,
5V-tolerant,
6-mA IOL
ATA control signal.
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