CY7C68310
Document 38-08030 Rev. *H
Page 18 of 34
0x0D
PIO Mode Selection
Bits (7:5)
0x90
PIO Mode Selection. The PIO mode reported back to the
device if the Override PIO Timing configuration bit is set.
mode 0
000
mode 1
001
mode 2
010
mode 3
011
mode 4
100
Skip Pin Reset
Bit (4)
Skip nATARST assertion. Setting this bit prevents the
CY7C68310 from asserting nATARST during initialization of
the ATA/ATAPI device. If this bit is set to ‘1’, SRST Enable
(address 0x09, bit 0) must also be set to ‘1’.
‘0’ = Allow nATARST assertion
‘1’ = Disable nATARST assertion
Reserved
Bits (3:0) – must be set to ‘0’.
0x0E
SYSIRQ User-defined Bits
Bits (7:3)
0x00
SYSIRQ USER_DEF[4:0] bits.
The value of these bits will be returned to the host via the
USB interrupt pipe as stated in Section 4.3.6.
General Purpose IO
Bits(2:0)
GPIO[2:0] pin values.
When the GPIO pins are configured as outputs, writing to
these bits will set the logic value of the GPIO pins to ‘0’ or ‘1’.
Reading this address, regardless of whether the GPIO pins
are set to input or output, returns the logic value from the
GPIO pins.
0x0F
ATAPI IRQ Disable
Bit (7)
0x07
Disables the use of the ATAIRQ signal with ATAPI devices.
‘0’ = ATAIRQ use enabled
‘1’ = ATAIRQ use disabled
Reserved
Bit (6) – must be set to ‘0’.
Int Reason Disable
Bit (5)
Setting to a ‘1’ causes CY7C68310 to ignore the contents of
the interrupt reason register when talking to an ATAPI
device.
HS Indicator Enable
Bit (4)
Enables GPIO2_nHS pin to indicate the current operating
speed of the device (if output is enabled).
‘0’ = normal GPIO operation
‘1’ = high-speed indicator enable
Reserved
Bit (3) – must be set to ‘1’.
General Purpose IO Pin
Enable
Bits (2:0)
GPIO[2:0] high-Z control. These bits have precedence over
bit 4 of this byte.
‘0’ = Output enabled (GPIO pin is an output).
‘1’ = high-Z (GPIO pin is an input).
Table 6-2. EEPROM Organization (continued)
I2C
Address
Field Name
Field Description
Required
I2C Data
Example
I2C Data
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